qemu-riscv.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, dbarboza@ventanamicro.com,
	wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
Date: Mon, 12 Jun 2023 11:18:42 +0800	[thread overview]
Message-ID: <ad06f409-5f14-75ea-9f9c-65a4b8596a3a@linux.alibaba.com> (raw)
In-Reply-To: <91eb4769-bfc3-23da-0a97-cd91a93ec936@iscas.ac.cn>


On 2023/6/12 11:16, Weiwei Li wrote:
>
> On 2023/6/12 11:08, LIU Zhiwei wrote:
>>
>> On 2023/5/29 20:17, Weiwei Li wrote:
>>> MPV and GVA bits are added by hypervisor extension to mstatus
>>> and mstatush (if MXLEN=32).
>>
>> Have you found the CSR field specifications for them, especially for 
>> GVA.
>
> Yeah.  in the section 9.4.1 of the privilege spec:
>
> "/The hypervisor extension adds two fields, MPV and GVA, to the 
> machine-level mstatus or mstatush CSR/".

I mean the WARL or other CSR field specifications here.

Zhiwei

>
> Regards,
>
> Weiwei Li
>
>>
>> Zhiwei
>>
>>>
>>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>>> ---
>>>   target/riscv/csr.c | 10 ++++------
>>>   1 file changed, 4 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>>> index 58499b5afc..6ac11d1f11 100644
>>> --- a/target/riscv/csr.c
>>> +++ b/target/riscv/csr.c
>>> @@ -1311,11 +1311,9 @@ static RISCVException 
>>> write_mstatus(CPURISCVState *env, int csrno,
>>>       }
>>>         if (xl != MXL_RV32 || env->debugger) {
>>> -        /*
>>> -         * RV32: MPV and GVA are not in mstatus. The current plan 
>>> is to
>>> -         * add them to mstatush. For now, we just don't support it.
>>> -         */
>>> -        mask |= MSTATUS_MPV | MSTATUS_GVA;
>>> +        if (riscv_has_ext(env, RVH)) {
>>> +            mask |= MSTATUS_MPV | MSTATUS_GVA;
>>> +        }
>>>           if ((val & MSTATUS64_UXL) != 0) {
>>>               mask |= MSTATUS64_UXL;
>>>           }
>>> @@ -1351,7 +1349,7 @@ static RISCVException 
>>> write_mstatush(CPURISCVState *env, int csrno,
>>>                                        target_ulong val)
>>>   {
>>>       uint64_t valh = (uint64_t)val << 32;
>>> -    uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
>>> +    uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | 
>>> MSTATUS_GVA : 0;
>>>         env->mstatus = (env->mstatus & ~mask) | (valh & mask);


  reply	other threads:[~2023-06-12  3:19 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-29 12:17 [PATCH 0/4] target/riscv: Fix mstatus related problems Weiwei Li
2023-05-29 12:17 ` [PATCH 1/4] target/riscv: Make MPV only work when MPP != PRV_M Weiwei Li
2023-05-30 20:23   ` Daniel Henrique Barboza
2023-05-31  0:27     ` Weiwei Li
2023-05-31  9:28       ` Daniel Henrique Barboza
2023-05-31  9:28   ` Daniel Henrique Barboza
2023-06-01  5:24   ` Alistair Francis
2023-06-12  2:45   ` LIU Zhiwei
2023-06-12  3:10     ` Weiwei Li
2023-06-12  3:30       ` LIU Zhiwei
2023-05-29 12:17 ` [PATCH 2/4] target/riscv: Remove check on mode for MPRV Weiwei Li
2023-05-30 20:25   ` Daniel Henrique Barboza
2023-05-31  9:28   ` Daniel Henrique Barboza
2023-06-01  5:27   ` Alistair Francis
2023-06-01  6:43     ` Weiwei Li
2023-06-01 23:03       ` Alistair Francis
2023-06-02  1:31         ` Weiwei Li
2023-06-02 21:01           ` Richard Henderson
2023-06-03 13:46             ` Weiwei Li
2023-05-29 12:17 ` [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled Weiwei Li
2023-05-30 20:26   ` Daniel Henrique Barboza
2023-06-01  5:28   ` Alistair Francis
2023-06-12  3:08   ` LIU Zhiwei
2023-06-12  3:16     ` Weiwei Li
2023-06-12  3:18       ` LIU Zhiwei [this message]
2023-06-12  4:35         ` Weiwei Li
2023-06-12  5:40           ` LIU Zhiwei
2023-06-12  7:27             ` Weiwei Li
2023-05-29 12:17 ` [PATCH 4/4] target/riscv: Remove redundant assignment to SXL Weiwei Li
2023-05-30 20:28   ` Daniel Henrique Barboza
2023-06-01  5:31   ` Alistair Francis
2023-06-12  5:55   ` LIU Zhiwei

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ad06f409-5f14-75ea-9f9c-65a4b8596a3a@linux.alibaba.com \
    --to=zhiwei_liu@linux.alibaba.com \
    --cc=alistair.francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=lazyparser@gmail.com \
    --cc=liweiwei@iscas.ac.cn \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=wangjunqiang@iscas.ac.cn \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).