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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.sourceforge.net
Cc: airlied@linux.ie, Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: [PATCH 3/7] drm/i915: remove duplicate PIPE*STAT bit definitions
Date: Fri, 26 Mar 2010 11:07:17 -0700	[thread overview]
Message-ID: <1269626841-10852-3-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1269626841-10852-1-git-send-email-jbarnes@virtuousgeek.org>

Just use the PIPEASTAT definitions, and kill a related, unused variable in
i915_irq_handler while we're there.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_irq.c |   23 +++++++++--------------
 drivers/gpu/drm/i915/i915_reg.h |   26 --------------------------
 2 files changed, 9 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5388354..eca0e5b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -170,7 +170,7 @@ void intel_enable_asle (struct drm_device *dev)
 		ironlake_enable_display_irq(dev_priv, DE_GSE);
 	else
 		i915_enable_pipestat(dev_priv, 1,
-				     I915_LEGACY_BLC_EVENT_ENABLE);
+				     PIPE_LEGACY_BLC_EVENT_ENABLE);
 }
 
 /**
@@ -832,9 +832,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	struct drm_i915_master_private *master_priv;
 	u32 iir, new_iir;
-	u32 pipea_stats, pipeb_stats;
-	u32 vblank_status;
-	u32 vblank_enable;
+	u32 pipea_stats, pipeb_stats, pipe_vblank_mask;
 	int vblank = 0;
 	unsigned long irqflags;
 	int irq_received;
@@ -847,13 +845,10 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
 	iir = I915_READ(IIR);
 
-	if (IS_I965G(dev)) {
-		vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
-		vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
-	} else {
-		vblank_status = I915_VBLANK_INTERRUPT_STATUS;
-		vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
-	}
+	if (IS_I965G(dev))
+		pipe_vblank_mask = PIPE_START_VBLANK_INTERRUPT_STATUS;
+	else
+		pipe_vblank_mask = PIPE_VBLANK_INTERRUPT_STATUS;
 
 	for (;;) {
 		irq_received = iir != 0;
@@ -933,19 +928,19 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 		if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 			intel_prepare_page_flip(dev, 1);
 
-		if (pipea_stats & vblank_status) {
+		if (pipea_stats & pipe_vblank_mask) {
 			vblank++;
 			drm_handle_vblank(dev, 0);
 			intel_finish_page_flip(dev, 0);
 		}
 
-		if (pipeb_stats & vblank_status) {
+		if (pipeb_stats & pipe_vblank_mask) {
 			vblank++;
 			drm_handle_vblank(dev, 1);
 			intel_finish_page_flip(dev, 1);
 		}
 
-		if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
+		if ((pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
 		    (iir & I915_ASLE_INTERRUPT))
 			opregion_asle_intr(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2720bc2..df20187 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -486,32 +486,6 @@
 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
 
-#define I915_FIFO_UNDERRUN_STATUS		(1UL<<31)
-#define I915_CRC_ERROR_ENABLE			(1UL<<29)
-#define I915_CRC_DONE_ENABLE			(1UL<<28)
-#define I915_GMBUS_EVENT_ENABLE			(1UL<<27)
-#define I915_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
-#define I915_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
-#define I915_DPST_EVENT_ENABLE			(1UL<<23)
-#define I915_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
-#define I915_ODD_FIELD_INTERRUPT_ENABLE		(1UL<<21)
-#define I915_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
-#define I915_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18)	/* 965 or later */
-#define I915_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
-#define I915_OVERLAY_UPDATED_ENABLE		(1UL<<16)
-#define I915_CRC_ERROR_INTERRUPT_STATUS		(1UL<<13)
-#define I915_CRC_DONE_INTERRUPT_STATUS		(1UL<<12)
-#define I915_GMBUS_INTERRUPT_STATUS		(1UL<<11)
-#define I915_VSYNC_INTERRUPT_STATUS		(1UL<<9)
-#define I915_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
-#define I915_DPST_EVENT_STATUS			(1UL<<7)
-#define I915_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
-#define I915_ODD_FIELD_INTERRUPT_STATUS		(1UL<<5)
-#define I915_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
-#define I915_START_VBLANK_INTERRUPT_STATUS	(1UL<<2)	/* 965 or later */
-#define I915_VBLANK_INTERRUPT_STATUS		(1UL<<1)
-#define I915_OVERLAY_UPDATED_STATUS		(1UL<<0)
-
 #define SRX_INDEX		0x3c4
 #define SRX_DATA		0x3c5
 #define SR01			1
-- 
1.6.1.3


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--

  parent reply	other threads:[~2010-03-26 18:07 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-03-26 18:07 [PATCH 1/7] drm: make sure vblank interrupts are disabled at DPMS time Jesse Barnes
2010-03-26 18:07 ` [PATCH 2/7] drm: delay vblank cleanup until after driver unload Jesse Barnes
2010-03-28 22:30   ` [Intel-gfx] " Kristian Høgsberg
2010-03-29  0:02     ` Dave Airlie
2010-03-29  0:09       ` Dave Airlie
2010-03-29 16:05       ` Jesse Barnes
2010-03-26 18:07 ` Jesse Barnes [this message]
2010-03-26 18:07 ` [PATCH 4/7] drm/i915: only check for enabled PIPE*STAT interrupts Jesse Barnes
2010-03-26 18:12   ` Jesse Barnes
2010-03-26 18:07 ` [PATCH 5/7] drm/i915: use vblank and vsync interrupts on 945 Jesse Barnes
2010-04-27 17:27   ` Jesse Barnes
2010-03-26 18:07 ` [PATCH 6/7] drm/i915: fix page flipping on gen3 Jesse Barnes
2010-03-26 20:41   ` Jesse Barnes
2010-04-05 21:07     ` Jesse Barnes
2010-03-26 18:07 ` [PATCH 7/7] drm/i915: cleanup mode setting before unmapping registers Jesse Barnes

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