From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
To: Intel Graphics <intel-gfx@lists.freedesktop.org>
Subject: [PATCH v2 4/9] drm/i915: Program correct m n tu register for Valleyview
Date: Thu, 27 Sep 2012 19:13:04 +0530 [thread overview]
Message-ID: <1348753389-30736-5-git-send-email-vijay.a.purushothaman@intel.com> (raw)
In-Reply-To: <1348753389-30736-1-git-send-email-vijay.a.purushothaman@intel.com>
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
drivers/gpu/drm/i915/intel_dp.c | 5 +++++
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 947c97d..68828e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -393,10 +393,10 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
};
static const intel_limit_t intel_limits_vlv_dp = {
- .dot = { .min = 162000, .max = 270000 },
- .vco = { .min = 5994000, .max = 4000000 },
+ .dot = { .min = 25000, .max = 270000 },
+ .vco = { .min = 4000000, .max = 6000000 },
.n = { .min = 1, .max = 7 },
- .m = { .min = 60, .max = 300 }, /* guess */
+ .m = { .min = 22, .max = 450 },
.m1 = { .min = 2, .max = 3 },
.m2 = { .min = 11, .max = 156 },
.p = { .min = 10, .max = 30 },
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index de8092a..c111c3f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -804,6 +804,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
+ } else if (IS_VALLEYVIEW(dev)) {
+ I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
} else {
I915_WRITE(PIPE_GMCH_DATA_M(pipe),
((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
--
1.7.9.5
next prev parent reply other threads:[~2012-09-27 13:41 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-27 13:43 [PATCH v2 0/9] Enable all display interfaces in Valleyview Vijay Purushothaman
2012-09-27 13:43 ` [PATCH v2 1/9] drm/i915: Set aux clk to 100MHz for Valleyview Vijay Purushothaman
2012-09-27 15:11 ` Jesse Barnes
2012-09-27 13:43 ` [PATCH v2 2/9] drm/i915: Fix SDVO IER and status bits " Vijay Purushothaman
2012-09-27 15:13 ` Jesse Barnes
2012-09-27 13:43 ` [PATCH v2 3/9] drm/i915: Add Valleyview lane control definitions Vijay Purushothaman
2012-09-27 15:17 ` Jesse Barnes
2012-09-27 13:43 ` Vijay Purushothaman [this message]
2012-09-27 15:18 ` [PATCH v2 4/9] drm/i915: Program correct m n tu register for Valleyview Jesse Barnes
2012-09-27 13:43 ` [PATCH v2 5/9] drm/i915: Disable CRT hotplug detection for valleyview Vijay Purushothaman
2012-09-27 15:20 ` Jesse Barnes
2012-09-28 14:51 ` Daniel Vetter
2012-09-27 15:34 ` Jesse Barnes
2012-09-27 13:43 ` [PATCH v2 6/9] drm/i915: Enable DisplayPort in Valleyview Vijay Purushothaman
2012-09-27 15:23 ` Jesse Barnes
2012-09-28 15:03 ` Daniel Vetter
2012-09-27 13:43 ` [PATCH v2 7/9] drm/i915: Add eDP support for Valleyview Vijay Purushothaman
2012-09-27 15:24 ` Jesse Barnes
2012-09-28 15:08 ` Daniel Vetter
2012-09-27 13:43 ` [PATCH v2 8/9] drm/i915: panel power sequencing for VLV eDP Vijay Purushothaman
2012-09-27 15:26 ` Jesse Barnes
2012-09-27 16:59 ` Daniel Vetter
2012-09-27 13:43 ` [PATCH v2 9/9] drm/i915: Fixup HDMI output on Valleyview Vijay Purushothaman
2012-09-27 15:26 ` Jesse Barnes
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