From: Tomasz Figa <t.figa@samsung.com>
To: linux-samsung-soc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org, kyungmin.park@samsung.com,
kgene.kim@samsung.com, m.szyprowski@samsung.com,
t.figa@samsung.com, s.nawrocki@samsung.com,
mturquette@linaro.org, thomas.abraham@linaro.org,
a.hajda@samsung.com, l.majewski@samsung.com
Subject: [PATCH 11/21] clk: samsung: exynos4: Add G3D clocks
Date: Wed, 27 Mar 2013 12:02:48 +0100 [thread overview]
Message-ID: <1364382178-25248-12-git-send-email-t.figa@samsung.com> (raw)
In-Reply-To: <1364382178-25248-1-git-send-email-t.figa@samsung.com>
This patch adds clocks needed for G3D block present on Exynos 4 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
.../devicetree/bindings/clock/exynos4-clock.txt | 4 ++++
drivers/clk/samsung/clk-exynos4.c | 22 ++++++++++++++--------
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 657b889..1863032 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -97,6 +97,7 @@ Exynos4 SoC and this is specified where applicable.
sclk_mipihsi 169 Exynos4412
sclk_mfc 170
sclk_pcm0 171
+ sclk_g3d 172
[Peripheral Clock Gates]
@@ -218,6 +219,9 @@ Exynos4 SoC and this is specified where applicable.
mout_cam1 389
mout_csis0 390
mout_csis1 391
+ mout_g3d0 392
+ mout_g3d1 393
+ mout_g3d 394
Example 1: An example of a clock controller node is listed below.
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 728ffaf..694b890 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -124,7 +124,7 @@ enum exynos4_clks {
sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
- sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0,
+ sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d,
/* gate clocks */
fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -142,7 +142,7 @@ enum exynos4_clks {
/* mux clocks */
mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
- mout_cam1, mout_csis0, mout_csis1,
+ mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
nr_clks,
};
@@ -296,8 +296,10 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
- MUX(none, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1),
- MUX(none, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+ MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
+ CLK_SET_RATE_PARENT, 0),
MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
};
@@ -329,7 +331,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
- MUX(none, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1),
+ MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
@@ -380,7 +383,8 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
- MUX(none, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1),
+ MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
@@ -415,7 +419,8 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
- DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+ DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
+ CLK_SET_RATE_PARENT, 0),
DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
@@ -501,7 +506,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0),
GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
- GATE(g3d, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
+ GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
+ CLK_SET_RATE_PARENT, 0),
GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
--
1.8.1.5
WARNING: multiple messages have this Message-ID (diff)
From: t.figa@samsung.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 11/21] clk: samsung: exynos4: Add G3D clocks
Date: Wed, 27 Mar 2013 12:02:48 +0100 [thread overview]
Message-ID: <1364382178-25248-12-git-send-email-t.figa@samsung.com> (raw)
In-Reply-To: <1364382178-25248-1-git-send-email-t.figa@samsung.com>
This patch adds clocks needed for G3D block present on Exynos 4 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
.../devicetree/bindings/clock/exynos4-clock.txt | 4 ++++
drivers/clk/samsung/clk-exynos4.c | 22 ++++++++++++++--------
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 657b889..1863032 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -97,6 +97,7 @@ Exynos4 SoC and this is specified where applicable.
sclk_mipihsi 169 Exynos4412
sclk_mfc 170
sclk_pcm0 171
+ sclk_g3d 172
[Peripheral Clock Gates]
@@ -218,6 +219,9 @@ Exynos4 SoC and this is specified where applicable.
mout_cam1 389
mout_csis0 390
mout_csis1 391
+ mout_g3d0 392
+ mout_g3d1 393
+ mout_g3d 394
Example 1: An example of a clock controller node is listed below.
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 728ffaf..694b890 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -124,7 +124,7 @@ enum exynos4_clks {
sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
- sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0,
+ sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d,
/* gate clocks */
fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -142,7 +142,7 @@ enum exynos4_clks {
/* mux clocks */
mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
- mout_cam1, mout_csis0, mout_csis1,
+ mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
nr_clks,
};
@@ -296,8 +296,10 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
- MUX(none, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1),
- MUX(none, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+ MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
+ CLK_SET_RATE_PARENT, 0),
MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
};
@@ -329,7 +331,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
- MUX(none, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1),
+ MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
@@ -380,7 +383,8 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
- MUX(none, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1),
+ MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
@@ -415,7 +419,8 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
- DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+ DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
+ CLK_SET_RATE_PARENT, 0),
DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
@@ -501,7 +506,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0),
GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
- GATE(g3d, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
+ GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
+ CLK_SET_RATE_PARENT, 0),
GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
--
1.8.1.5
next prev parent reply other threads:[~2013-03-27 11:06 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-27 11:02 [PATCH 00/21] Various fixes and extensions to Exynos4 clock driver Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 01/21] clk: samsung: exynos4: Correct sclk_mfc clock definition Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 02/21] clk: samsung: exynos4: Use mout_mpll_user_* on Exynos4x12 Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 03/21] clk: samsung: exynos4: Add missing mout_mipihsi clock Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 04/21] clk: samsung: exynos4: Add missing sclk_audio0 clock Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 05/21] clk: samsung: exynos4: Export sclk_pcm0 Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 06/21] clk: samsung: exynos4: Move dac and mixer to Exynos4210-specific clocks Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 07/21] clk: samsung: exynos4: Export clocks used by exynos cpufreq drivers Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 08/21] clk: samsung: pll: Remove unimplemented ops Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 09/21] clk: samsung: exynos4: Export mout_core clock of Exynos4210 Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 10/21] clk: samsung: exynos4: Add camera related clock definitions Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa [this message]
2013-03-27 11:02 ` [PATCH 11/21] clk: samsung: exynos4: Add G3D clocks Tomasz Figa
2013-03-27 11:02 ` [PATCH 12/21] clk: samsung: exynos4: Add missing CMU_TOP and ISP clocks Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 13/21] clk: samsung: exynos4: Add missing mout_sata on Exynos4210 Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 14/21] clk: samsung: exynos4: Define {E,V}PLL registers Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 15/21] clk: samsung: exynos4: Use SRC_MASK_PERIL{0,1} definitions Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 16/21] clk: samsung: exynos4: Remove SoC-specific registers from save list Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 17/21] clk: samsung: exynos4: Add E4210 prefix to LCD1 clock registers Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 18/21] clk: samsung: exynos4: Add E4210 prefix to GATE_IP_PERIR register Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 19/21] clk: samsung: exynos4: Remove E4X12 prefix from SRC_DMC register Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 20/21] clk: samsung: exynos4: Add missing registers to suspend save list Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-27 11:02 ` [PATCH 21/21] clk: samsung: exynos4: Add support for SoC-specific register " Tomasz Figa
2013-03-27 11:02 ` Tomasz Figa
2013-03-30 10:03 ` [PATCH 00/21] Various fixes and extensions to Exynos4 clock driver Thomas Abraham
2013-03-30 10:03 ` Thomas Abraham
2013-03-30 11:30 ` Tomasz Figa
2013-03-30 11:30 ` Tomasz Figa
2013-04-02 8:30 ` Kukjin Kim
2013-04-02 8:30 ` Kukjin Kim
2013-04-03 22:01 ` Mike Turquette
2013-04-03 22:01 ` Mike Turquette
2013-04-04 0:36 ` Kukjin Kim
2013-04-04 0:36 ` Kukjin Kim
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