From: Tomasz Figa <t.figa@samsung.com> To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kyungmin.park@samsung.com, kgene.kim@samsung.com, m.szyprowski@samsung.com, t.figa@samsung.com, s.nawrocki@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, a.hajda@samsung.com, l.majewski@samsung.com Subject: [PATCH 14/21] clk: samsung: exynos4: Define {E,V}PLL registers Date: Wed, 27 Mar 2013 12:02:51 +0100 [thread overview] Message-ID: <1364382178-25248-15-git-send-email-t.figa@samsung.com> (raw) In-Reply-To: <1364382178-25248-1-git-send-email-t.figa@samsung.com> This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- drivers/clk/samsung/clk-exynos4.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 959402f..8ce3b25 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -25,6 +25,14 @@ #define E4X12_GATE_IP_IMAGE 0x4930 #define GATE_IP_RIGHTBUS 0x8800 #define E4X12_GATE_IP_PERIR 0x8960 +#define EPLL_LOCK 0xc010 +#define VPLL_LOCK 0xc020 +#define EPLL_CON0 0xc110 +#define EPLL_CON1 0xc114 +#define EPLL_CON2 0xc118 +#define VPLL_CON0 0xc120 +#define VPLL_CON1 0xc124 +#define VPLL_CON2 0xc128 #define SRC_TOP0 0xc210 #define SRC_TOP1 0xc214 #define SRC_CAM 0xc220 @@ -968,18 +976,18 @@ void __init exynos4_clk_init(struct device_node *np) mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll", reg_base + E4210_MPLL_CON0, pll_4508); epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll", - reg_base + 0xc110, pll_4600); + reg_base + EPLL_CON0, pll_4600); vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", - reg_base + 0xc120, pll_4650c); + reg_base + VPLL_CON0, pll_4650c); } else { apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", reg_base + APLL_CON0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", reg_base + E4X12_MPLL_CON0); epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", - reg_base + 0xc110); + reg_base + EPLL_CON0); vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll", - reg_base + 0xc120); + reg_base + VPLL_CON0); } samsung_clk_add_lookup(apll, fout_apll); -- 1.8.1.5
WARNING: multiple messages have this Message-ID (diff)
From: t.figa@samsung.com (Tomasz Figa) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 14/21] clk: samsung: exynos4: Define {E,V}PLL registers Date: Wed, 27 Mar 2013 12:02:51 +0100 [thread overview] Message-ID: <1364382178-25248-15-git-send-email-t.figa@samsung.com> (raw) In-Reply-To: <1364382178-25248-1-git-send-email-t.figa@samsung.com> This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- drivers/clk/samsung/clk-exynos4.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 959402f..8ce3b25 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -25,6 +25,14 @@ #define E4X12_GATE_IP_IMAGE 0x4930 #define GATE_IP_RIGHTBUS 0x8800 #define E4X12_GATE_IP_PERIR 0x8960 +#define EPLL_LOCK 0xc010 +#define VPLL_LOCK 0xc020 +#define EPLL_CON0 0xc110 +#define EPLL_CON1 0xc114 +#define EPLL_CON2 0xc118 +#define VPLL_CON0 0xc120 +#define VPLL_CON1 0xc124 +#define VPLL_CON2 0xc128 #define SRC_TOP0 0xc210 #define SRC_TOP1 0xc214 #define SRC_CAM 0xc220 @@ -968,18 +976,18 @@ void __init exynos4_clk_init(struct device_node *np) mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll", reg_base + E4210_MPLL_CON0, pll_4508); epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll", - reg_base + 0xc110, pll_4600); + reg_base + EPLL_CON0, pll_4600); vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", - reg_base + 0xc120, pll_4650c); + reg_base + VPLL_CON0, pll_4650c); } else { apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", reg_base + APLL_CON0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", reg_base + E4X12_MPLL_CON0); epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", - reg_base + 0xc110); + reg_base + EPLL_CON0); vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll", - reg_base + 0xc120); + reg_base + VPLL_CON0); } samsung_clk_add_lookup(apll, fout_apll); -- 1.8.1.5
next prev parent reply other threads:[~2013-03-27 11:07 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-03-27 11:02 [PATCH 00/21] Various fixes and extensions to Exynos4 clock driver Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 01/21] clk: samsung: exynos4: Correct sclk_mfc clock definition Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 02/21] clk: samsung: exynos4: Use mout_mpll_user_* on Exynos4x12 Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 03/21] clk: samsung: exynos4: Add missing mout_mipihsi clock Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 04/21] clk: samsung: exynos4: Add missing sclk_audio0 clock Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 05/21] clk: samsung: exynos4: Export sclk_pcm0 Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 06/21] clk: samsung: exynos4: Move dac and mixer to Exynos4210-specific clocks Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 07/21] clk: samsung: exynos4: Export clocks used by exynos cpufreq drivers Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 08/21] clk: samsung: pll: Remove unimplemented ops Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 09/21] clk: samsung: exynos4: Export mout_core clock of Exynos4210 Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 10/21] clk: samsung: exynos4: Add camera related clock definitions Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 11/21] clk: samsung: exynos4: Add G3D clocks Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 12/21] clk: samsung: exynos4: Add missing CMU_TOP and ISP clocks Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 13/21] clk: samsung: exynos4: Add missing mout_sata on Exynos4210 Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa [this message] 2013-03-27 11:02 ` [PATCH 14/21] clk: samsung: exynos4: Define {E,V}PLL registers Tomasz Figa 2013-03-27 11:02 ` [PATCH 15/21] clk: samsung: exynos4: Use SRC_MASK_PERIL{0,1} definitions Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 16/21] clk: samsung: exynos4: Remove SoC-specific registers from save list Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 17/21] clk: samsung: exynos4: Add E4210 prefix to LCD1 clock registers Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 18/21] clk: samsung: exynos4: Add E4210 prefix to GATE_IP_PERIR register Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 19/21] clk: samsung: exynos4: Remove E4X12 prefix from SRC_DMC register Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 20/21] clk: samsung: exynos4: Add missing registers to suspend save list Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 21/21] clk: samsung: exynos4: Add support for SoC-specific register " Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-30 10:03 ` [PATCH 00/21] Various fixes and extensions to Exynos4 clock driver Thomas Abraham 2013-03-30 10:03 ` Thomas Abraham 2013-03-30 11:30 ` Tomasz Figa 2013-03-30 11:30 ` Tomasz Figa 2013-04-02 8:30 ` Kukjin Kim 2013-04-02 8:30 ` Kukjin Kim 2013-04-03 22:01 ` Mike Turquette 2013-04-03 22:01 ` Mike Turquette 2013-04-04 0:36 ` Kukjin Kim 2013-04-04 0:36 ` Kukjin Kim
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