From: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> To: Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>, Sebastian Hesselbarth <sebastian.hesselbarth-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>, Gregory Clement <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> Cc: linux ARM <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>, Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: [Patch v3 10/23] ARM: MM: Add DT binding for Feroceon L2 cache Date: Wed, 19 Feb 2014 15:12:41 +0100 [thread overview] Message-ID: <1392819174-11634-11-git-send-email-andrew@lunn.ch> (raw) In-Reply-To: <1392819174-11634-1-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org --- v2: Change compatible strings to follow l2x0 convention Only expect register for kirkwood-cache. Default to write through if no DT node. Rename writethrough to wt-override to follow l2cc binding. Split kirkwood.dtsi change into a patch of its own. v3 Remove wt-override from the binding Respect CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH --- .../devicetree/bindings/arm/mrvl/feroceon.txt | 16 ++++++++ arch/arm/include/asm/hardware/cache-feroceon-l2.h | 2 + arch/arm/mach-kirkwood/board-dt.c | 18 ++------- arch/arm/mm/cache-feroceon-l2.c | 43 ++++++++++++++++++++++ 4 files changed, 64 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mrvl/feroceon.txt diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt new file mode 100644 index 000000000000..0d244b999d10 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt @@ -0,0 +1,16 @@ +* Marvell Feroceon Cache + +Required properties: +- compatible : Should be either "marvell,feroceon-cache" or + "marvell,kirkwood-cache". + +Optional properties: +- reg : Address of the L2 cache control register. Mandatory for + "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" + + +Example: + l2: l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; diff --git a/arch/arm/include/asm/hardware/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h index 8edd330aabf6..12e1588dc4f1 100644 --- a/arch/arm/include/asm/hardware/cache-feroceon-l2.h +++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h @@ -9,3 +9,5 @@ */ extern void __init feroceon_l2_init(int l2_wt_override); +extern int __init feroceon_of_init(void); + diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 29c246858d5a..ec0702c02d6c 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -42,19 +42,6 @@ static void __init kirkwood_map_io(void) iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); } -static void __init kirkwood_l2_init(void) -{ -#ifdef CONFIG_CACHE_FEROCEON_L2 -#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH - writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); - feroceon_l2_init(1); -#else - writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG); - feroceon_l2_init(0); -#endif -#endif -} - static struct resource kirkwood_cpufreq_resources[] = { [0] = { .start = CPU_CONTROL_PHYS, @@ -211,8 +198,9 @@ static void __init kirkwood_dt_init(void) BUG_ON(mvebu_mbus_dt_init()); - kirkwood_l2_init(); - +#ifdef CONFIG_CACHE_FEROCEON_L2 + feroceon_of_init(); +#endif kirkwood_cpufreq_init(); kirkwood_cpuidle_init(); diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 898362e7972b..8dc1a2b5a8ed 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -13,11 +13,16 @@ */ #include <linux/init.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <linux/highmem.h> +#include <linux/io.h> #include <asm/cacheflush.h> #include <asm/cp15.h> #include <asm/hardware/cache-feroceon-l2.h> +#define L2_WRITETHROUGH_KIRKWOOD BIT(4) + /* * Low-level cache maintenance operations. * @@ -350,3 +355,41 @@ void __init feroceon_l2_init(int __l2_wt_override) printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n", l2_wt_override ? ", in WT override mode" : ""); } +#ifdef CONFIG_OF +static const struct of_device_id feroceon_ids[] __initconst = { + { .compatible = "marvell,kirkwood-cache"}, + { .compatible = "marvell,feroceon-cache"}, + {} +}; + +int __init feroceon_of_init(void) +{ + struct device_node *node; + void __iomem *base; + bool l2_wt_override = false; + struct resource res; + +#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) + l2_wt_override = true; +#endif + + node = of_find_matching_node(NULL, feroceon_ids); + if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) { + if (of_address_to_resource(node, 0, &res)) + return -ENODEV; + + base = ioremap(res.start, resource_size(&res)); + if (!base) + return -ENOMEM; + + if (l2_wt_override) + writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base); + else + writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base); + } + + feroceon_l2_init(l2_wt_override); + + return 0; +} +#endif -- 1.8.5.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: andrew@lunn.ch (Andrew Lunn) To: linux-arm-kernel@lists.infradead.org Subject: [Patch v3 10/23] ARM: MM: Add DT binding for Feroceon L2 cache Date: Wed, 19 Feb 2014 15:12:41 +0100 [thread overview] Message-ID: <1392819174-11634-11-git-send-email-andrew@lunn.ch> (raw) In-Reply-To: <1392819174-11634-1-git-send-email-andrew@lunn.ch> Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> cc: devicetree at vger.kernel.org --- v2: Change compatible strings to follow l2x0 convention Only expect register for kirkwood-cache. Default to write through if no DT node. Rename writethrough to wt-override to follow l2cc binding. Split kirkwood.dtsi change into a patch of its own. v3 Remove wt-override from the binding Respect CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH --- .../devicetree/bindings/arm/mrvl/feroceon.txt | 16 ++++++++ arch/arm/include/asm/hardware/cache-feroceon-l2.h | 2 + arch/arm/mach-kirkwood/board-dt.c | 18 ++------- arch/arm/mm/cache-feroceon-l2.c | 43 ++++++++++++++++++++++ 4 files changed, 64 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mrvl/feroceon.txt diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt new file mode 100644 index 000000000000..0d244b999d10 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt @@ -0,0 +1,16 @@ +* Marvell Feroceon Cache + +Required properties: +- compatible : Should be either "marvell,feroceon-cache" or + "marvell,kirkwood-cache". + +Optional properties: +- reg : Address of the L2 cache control register. Mandatory for + "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" + + +Example: + l2: l2-cache at 20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; diff --git a/arch/arm/include/asm/hardware/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h index 8edd330aabf6..12e1588dc4f1 100644 --- a/arch/arm/include/asm/hardware/cache-feroceon-l2.h +++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h @@ -9,3 +9,5 @@ */ extern void __init feroceon_l2_init(int l2_wt_override); +extern int __init feroceon_of_init(void); + diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 29c246858d5a..ec0702c02d6c 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -42,19 +42,6 @@ static void __init kirkwood_map_io(void) iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); } -static void __init kirkwood_l2_init(void) -{ -#ifdef CONFIG_CACHE_FEROCEON_L2 -#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH - writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); - feroceon_l2_init(1); -#else - writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG); - feroceon_l2_init(0); -#endif -#endif -} - static struct resource kirkwood_cpufreq_resources[] = { [0] = { .start = CPU_CONTROL_PHYS, @@ -211,8 +198,9 @@ static void __init kirkwood_dt_init(void) BUG_ON(mvebu_mbus_dt_init()); - kirkwood_l2_init(); - +#ifdef CONFIG_CACHE_FEROCEON_L2 + feroceon_of_init(); +#endif kirkwood_cpufreq_init(); kirkwood_cpuidle_init(); diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 898362e7972b..8dc1a2b5a8ed 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -13,11 +13,16 @@ */ #include <linux/init.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <linux/highmem.h> +#include <linux/io.h> #include <asm/cacheflush.h> #include <asm/cp15.h> #include <asm/hardware/cache-feroceon-l2.h> +#define L2_WRITETHROUGH_KIRKWOOD BIT(4) + /* * Low-level cache maintenance operations. * @@ -350,3 +355,41 @@ void __init feroceon_l2_init(int __l2_wt_override) printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n", l2_wt_override ? ", in WT override mode" : ""); } +#ifdef CONFIG_OF +static const struct of_device_id feroceon_ids[] __initconst = { + { .compatible = "marvell,kirkwood-cache"}, + { .compatible = "marvell,feroceon-cache"}, + {} +}; + +int __init feroceon_of_init(void) +{ + struct device_node *node; + void __iomem *base; + bool l2_wt_override = false; + struct resource res; + +#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) + l2_wt_override = true; +#endif + + node = of_find_matching_node(NULL, feroceon_ids); + if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) { + if (of_address_to_resource(node, 0, &res)) + return -ENODEV; + + base = ioremap(res.start, resource_size(&res)); + if (!base) + return -ENOMEM; + + if (l2_wt_override) + writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base); + else + writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base); + } + + feroceon_l2_init(l2_wt_override); + + return 0; +} +#endif -- 1.8.5.3
next prev parent reply other threads:[~2014-02-19 14:12 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-02-19 14:12 [Patch v3 00/23] Move DT kirkwood into mach-mvebu Andrew Lunn 2014-02-19 14:12 ` [Patch v3 01/23] ARM: Kirkwood: Give pm.c its own header file Andrew Lunn 2014-02-19 14:12 ` [Patch v3 02/23] irqchip: Orion: Fix getting generic chip pointer Andrew Lunn 2014-02-19 14:12 ` [Patch v3 03/23] ARM: Kirkwood: Convert mv88f6281gtw_ge switch setup to DT Andrew Lunn 2014-02-19 14:12 ` [Patch v3 04/23] ARM: Kirkwood: Drop printing the SoC type and revision Andrew Lunn 2014-02-19 14:12 ` [Patch v3 05/23] ARM: Kirkwood: Seperate board-dt from common and pcie code Andrew Lunn 2014-02-19 14:12 ` [Patch v3 06/23] ARM: Kirkwood: ioremap the cpu_config register before using it Andrew Lunn 2014-02-19 14:12 ` [Patch v3 07/23] ARM: Kirkwood: ioremap memory control register Andrew Lunn 2014-02-19 14:12 ` [Patch v3 08/23] ARM: MVEBU: Add ARCH_MULTI_V7 to SoCs Andrew Lunn 2014-02-19 14:12 ` [Patch v3 09/23] ARM: Orion: Move cache-feroceon-l2.h out of plat-orion Andrew Lunn [not found] ` <1392819174-11634-1-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> 2014-02-19 14:12 ` Andrew Lunn [this message] 2014-02-19 14:12 ` [Patch v3 10/23] ARM: MM: Add DT binding for Feroceon L2 cache Andrew Lunn [not found] ` <1392819174-11634-11-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> 2014-02-19 18:17 ` Jason Cooper 2014-02-19 18:17 ` Jason Cooper 2014-02-19 14:12 ` [Patch v3 11/23] ARM: Kirkwood: Instantiate L2 cache from DT Andrew Lunn 2014-02-19 14:12 ` [Patch v3 12/23] ARM: Fix default CPU selection for ARCH_MULTI_V5 Andrew Lunn 2014-02-19 14:12 ` [Patch v3 13/23] ARM: Fix MULTI_TLB for feroceon Andrew Lunn 2014-02-19 14:12 ` [Patch v3 14/23] ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBU Andrew Lunn 2014-02-19 14:12 ` [Patch v3 15/23] ARM: Move kirkwood DT boards into mach-mvebu Andrew Lunn 2014-02-19 14:12 ` [Patch v3 16/23] ARM: MVEBU: Let kirkwood use the system controller for restart Andrew Lunn 2014-02-19 14:12 ` [Patch v3 17/23] ARM: MVEBU: Instantiate system controller in kirkwood.dtsi Andrew Lunn 2014-02-19 14:12 ` [Patch v3 18/23] drivers: Enable building of Kirkwood drivers for mach-mvebu Andrew Lunn 2014-02-20 4:00 ` Mark Brown 2014-02-20 5:26 ` Kishon Vijay Abraham I 2014-02-20 8:55 ` Daniel Lezcano 2014-02-19 14:12 ` [Patch v3 19/23] ARM: MVEBU: Enable mvebu-soc-id on Kirkwood Andrew Lunn 2014-02-19 14:12 ` [Patch v3 20/23] ARM: config: Add a multi_v5_defconfig Andrew Lunn 2014-02-19 14:19 ` Alexander Shiyan 2014-02-19 14:24 ` Andrew Lunn 2014-02-19 14:54 ` Arnd Bergmann 2014-02-19 15:08 ` Alexander Shiyan 2014-02-19 15:54 ` Arnd Bergmann 2014-02-19 15:59 ` Alexander Shiyan 2014-02-19 16:42 ` Andrew Lunn 2014-02-19 14:12 ` [Patch v3 21/23] ARM: MVEBU: Simplifiy headers and make local Andrew Lunn 2014-02-19 18:20 ` Jason Cooper 2014-02-19 14:12 ` [Patch v3 22/23] ARM: config: Add mvebu_v5_defconfig Andrew Lunn 2014-02-19 14:12 ` [Patch v3 23/23] ARM: Kirkwood: Remove DT support Andrew Lunn
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