From: Thomas Abraham <ta.omasab@gmail.com> To: cpufreq@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, shawn.guo@linaro.org, devicetree@vger.kernel.org, rjw@rjwysocki.net, linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, t.figa@samsung.com, l.majewski@samsung.com, viresh.kumar@linaro.org, heiko@sntech.de, thomas.ab@samsung.com, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org> Subject: [PATCH v4 4/8] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 Date: Wed, 14 May 2014 06:41:12 +0530 [thread overview] Message-ID: <1400029876-5830-5-git-send-email-thomas.ab@samsung.com> (raw) In-Reply-To: <1400029876-5830-1-git-send-email-thomas.ab@samsung.com> From; Thomas Abraham <thomas.ab@samsung.com> The clock blocks within the CMU_CPU clock domain are put together into a new composite clock type called the cpu clock. This clock type requires configuration data that will be atomically programmed in the multiple clock blocks encapsulated within the cpu clock type when the parent clock frequency is changed. This configuration data is held in the clock controller node. Update clock binding documentation about this configuration data format for Samsung Exynos4 and Exynos5 platforms. Cc: Tomasz Figa <t.figa@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: <devicetree@vger.kernel.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- .../devicetree/bindings/clock/exynos4-clock.txt | 37 ++++++++++++++++++++ .../devicetree/bindings/clock/exynos5250-clock.txt | 36 +++++++++++++++++++ 2 files changed, 73 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index f5a5b19..0934e02 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -15,6 +15,35 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + - for Exynos4210 and Exynos4212 based platforms: + cell #1: arm clock parent frequency + cell #2 ~ cell 9#: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio. + + - for Exynos4412 based platforms: + cell #1: expected arm clock parent frequency + cell #2 ~ cell #10: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio, cores_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property depends on + the SoC type. + + - for Exynos4210 and Exynos4212: the value should be 9. + - for Exynos4412: the value should be 10. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -28,6 +57,14 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1200000 3 7 3 4 1 7 5 0>, + <1000000 3 7 3 4 1 7 4 0>, + < 800000 3 7 3 3 1 7 3 0>, + < 500000 3 7 3 3 1 7 3 0>, + < 400000 3 7 3 3 1 7 3 0>, + < 200000 1 3 1 1 1 0 3 0>; }; Example 2: UART controller node that consumes the clock generated by the clock diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 536eacd..3d63d09 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -13,6 +13,24 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + cell #1: expected arm clock parent frequency + cell #2 ~ cell #9: value of clock divider in the following order + cpud_ratio, acp_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property should be 9. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -26,6 +44,24 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1700000 3 7 7 7 3 5 0 2>, + <1600000 3 7 7 7 1 4 0 2>, + <1500000 2 7 7 7 1 4 0 2>, + <1400000 2 7 7 6 1 4 0 2>, + <1300000 2 7 7 6 1 3 0 2>, + <1200000 2 7 7 5 1 3 0 2>, + <1100000 3 7 7 5 1 3 0 2>, + <1000000 1 7 7 4 1 2 0 2>, + < 900000 1 7 7 4 1 2 0 2>, + < 800000 1 7 7 4 1 2 0 2>, + < 700000 1 7 7 3 1 1 0 2>, + < 600000 1 7 7 3 1 1 0 2>, + < 500000 1 7 7 2 1 1 0 2>, + < 400000 1 7 7 2 1 1 0 2>, + < 300000 1 7 7 1 1 1 0 2>, + < 200000 1 7 7 1 1 1 0 2>; }; Example 2: UART controller node that consumes the clock generated by the clock -- 1.7.4.4
WARNING: multiple messages have this Message-ID (diff)
From: ta.omasab@gmail.com (Thomas Abraham) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/8] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 Date: Wed, 14 May 2014 06:41:12 +0530 [thread overview] Message-ID: <1400029876-5830-5-git-send-email-thomas.ab@samsung.com> (raw) In-Reply-To: <1400029876-5830-1-git-send-email-thomas.ab@samsung.com> From; Thomas Abraham <thomas.ab@samsung.com> The clock blocks within the CMU_CPU clock domain are put together into a new composite clock type called the cpu clock. This clock type requires configuration data that will be atomically programmed in the multiple clock blocks encapsulated within the cpu clock type when the parent clock frequency is changed. This configuration data is held in the clock controller node. Update clock binding documentation about this configuration data format for Samsung Exynos4 and Exynos5 platforms. Cc: Tomasz Figa <t.figa@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: <devicetree@vger.kernel.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- .../devicetree/bindings/clock/exynos4-clock.txt | 37 ++++++++++++++++++++ .../devicetree/bindings/clock/exynos5250-clock.txt | 36 +++++++++++++++++++ 2 files changed, 73 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index f5a5b19..0934e02 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -15,6 +15,35 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + - for Exynos4210 and Exynos4212 based platforms: + cell #1: arm clock parent frequency + cell #2 ~ cell 9#: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio. + + - for Exynos4412 based platforms: + cell #1: expected arm clock parent frequency + cell #2 ~ cell #10: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio, cores_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property depends on + the SoC type. + + - for Exynos4210 and Exynos4212: the value should be 9. + - for Exynos4412: the value should be 10. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -28,6 +57,14 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1200000 3 7 3 4 1 7 5 0>, + <1000000 3 7 3 4 1 7 4 0>, + < 800000 3 7 3 3 1 7 3 0>, + < 500000 3 7 3 3 1 7 3 0>, + < 400000 3 7 3 3 1 7 3 0>, + < 200000 1 3 1 1 1 0 3 0>; }; Example 2: UART controller node that consumes the clock generated by the clock diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 536eacd..3d63d09 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -13,6 +13,24 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + cell #1: expected arm clock parent frequency + cell #2 ~ cell #9: value of clock divider in the following order + cpud_ratio, acp_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property should be 9. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -26,6 +44,24 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1700000 3 7 7 7 3 5 0 2>, + <1600000 3 7 7 7 1 4 0 2>, + <1500000 2 7 7 7 1 4 0 2>, + <1400000 2 7 7 6 1 4 0 2>, + <1300000 2 7 7 6 1 3 0 2>, + <1200000 2 7 7 5 1 3 0 2>, + <1100000 3 7 7 5 1 3 0 2>, + <1000000 1 7 7 4 1 2 0 2>, + < 900000 1 7 7 4 1 2 0 2>, + < 800000 1 7 7 4 1 2 0 2>, + < 700000 1 7 7 3 1 1 0 2>, + < 600000 1 7 7 3 1 1 0 2>, + < 500000 1 7 7 2 1 1 0 2>, + < 400000 1 7 7 2 1 1 0 2>, + < 300000 1 7 7 1 1 1 0 2>, + < 200000 1 7 7 1 1 1 0 2>; }; Example 2: UART controller node that consumes the clock generated by the clock -- 1.7.4.4
next prev parent reply other threads:[~2014-05-14 1:11 UTC|newest] Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-05-14 1:11 [PATCH v4 0/8] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-14 1:11 ` [PATCH v4 1/8] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-14 3:46 ` Viresh Kumar 2014-05-14 3:46 ` Viresh Kumar 2014-05-14 6:17 ` Lukasz Majewski 2014-05-14 6:17 ` Lukasz Majewski 2014-05-14 6:20 ` Viresh Kumar 2014-05-14 6:20 ` Viresh Kumar 2014-05-14 13:43 ` Thomas Abraham 2014-05-14 13:43 ` Thomas Abraham 2014-05-14 13:50 ` Viresh Kumar 2014-05-14 13:50 ` Viresh Kumar 2014-05-14 14:18 ` Thomas Abraham 2014-05-14 14:18 ` Thomas Abraham 2014-05-14 14:20 ` Viresh Kumar 2014-05-14 14:20 ` Viresh Kumar 2014-05-14 1:11 ` [PATCH v4 2/8] clk: samsung: change scope of samsung clock lock to global Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-14 3:50 ` Viresh Kumar 2014-05-14 3:50 ` Viresh Kumar 2014-05-14 13:26 ` Thomas Abraham 2014-05-14 13:26 ` Thomas Abraham 2014-05-16 12:30 ` Tomasz Figa 2014-05-16 12:30 ` Tomasz Figa 2014-05-14 1:11 ` [PATCH v4 3/8] clk: samsung: add infrastructure to register cpu clocks Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-15 18:18 ` Doug Anderson 2014-05-15 18:18 ` Doug Anderson 2014-05-15 19:17 ` Heiko Stübner 2014-05-15 19:17 ` Heiko Stübner 2014-05-15 19:36 ` Doug Anderson 2014-05-15 19:36 ` Doug Anderson 2014-05-15 19:36 ` Doug Anderson 2014-05-15 20:12 ` Heiko Stübner 2014-05-15 20:12 ` Heiko Stübner 2014-05-15 20:26 ` Doug Anderson 2014-05-15 20:26 ` Doug Anderson 2014-05-16 4:55 ` Thomas Abraham 2014-05-16 4:55 ` Thomas Abraham 2014-05-16 17:17 ` Tomasz Figa 2014-05-16 17:17 ` Tomasz Figa 2014-05-23 14:41 ` Thomas Abraham 2014-05-23 14:41 ` Thomas Abraham 2014-05-23 14:50 ` Tomasz Figa 2014-05-23 14:50 ` Tomasz Figa 2014-05-14 1:11 ` Thomas Abraham [this message] 2014-05-14 1:11 ` [PATCH v4 4/8] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 Thomas Abraham 2014-05-16 23:24 ` Tomasz Figa 2014-05-16 23:24 ` Tomasz Figa 2014-05-17 0:00 ` Tomasz Figa 2014-05-17 0:00 ` Tomasz Figa 2014-05-26 6:05 ` Thomas Abraham 2014-05-26 6:05 ` Thomas Abraham 2014-05-26 11:02 ` Tomasz Figa 2014-05-26 11:02 ` Tomasz Figa 2014-05-14 1:11 ` [PATCH v4 5/8] clk: exynos: use cpu-clock provider type to represent arm clock Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-14 21:37 ` Mike Turquette 2014-05-14 21:37 ` Mike Turquette 2014-05-15 7:48 ` Thomas Abraham 2014-05-15 7:48 ` Thomas Abraham 2014-05-15 8:10 ` Lukasz Majewski 2014-05-15 8:10 ` Lukasz Majewski 2014-05-15 9:59 ` Thomas Abraham 2014-05-15 9:59 ` Thomas Abraham 2014-05-16 5:14 ` Thomas Abraham 2014-05-16 5:14 ` Thomas Abraham 2014-05-16 23:57 ` Tomasz Figa 2014-05-16 23:57 ` Tomasz Figa 2014-05-14 1:11 ` [PATCH v4 6/8] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-16 23:16 ` Tomasz Figa 2014-05-16 23:16 ` Tomasz Figa 2014-05-14 1:11 ` [PATCH v4 7/8] ARM: Exynos: switch to using generic cpufreq-cpu0 driver Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-14 12:50 ` Arnd Bergmann 2014-05-14 12:50 ` Arnd Bergmann 2014-05-14 13:05 ` Viresh Kumar 2014-05-14 13:05 ` Viresh Kumar 2014-05-14 13:11 ` Heiko Stübner 2014-05-14 13:11 ` Heiko Stübner 2014-05-14 13:14 ` Viresh Kumar 2014-05-14 13:14 ` Viresh Kumar 2014-05-14 13:14 ` Viresh Kumar 2014-05-14 13:18 ` Arnd Bergmann 2014-05-14 13:18 ` Arnd Bergmann 2014-05-14 13:45 ` Rob Herring 2014-05-14 13:45 ` Rob Herring 2014-05-14 13:45 ` Rob Herring 2014-05-14 14:33 ` Arnd Bergmann 2014-05-14 14:33 ` Arnd Bergmann 2014-07-08 5:15 ` Viresh Kumar 2014-07-08 5:15 ` Viresh Kumar 2014-05-14 14:03 ` Thomas Abraham 2014-05-14 14:03 ` Thomas Abraham 2014-05-14 14:03 ` Thomas Abraham 2014-05-14 14:09 ` Sudeep Holla 2014-05-14 14:09 ` Sudeep Holla 2014-05-14 14:09 ` Sudeep Holla 2014-05-14 14:09 ` Thomas Abraham 2014-05-14 14:09 ` Thomas Abraham 2014-05-17 0:04 ` Tomasz Figa 2014-05-17 0:04 ` Tomasz Figa 2014-05-14 1:11 ` [PATCH v4 8/8] cpufreq: exynos: remove all exynos specific cpufreq driver support Thomas Abraham 2014-05-14 1:11 ` Thomas Abraham 2014-05-14 3:57 ` Viresh Kumar 2014-05-14 3:57 ` Viresh Kumar 2014-05-14 7:20 ` Lukasz Majewski 2014-05-14 7:20 ` Lukasz Majewski 2014-05-14 13:53 ` Thomas Abraham 2014-05-14 13:53 ` Thomas Abraham 2014-05-14 12:51 ` [PATCH v4 0/8] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Arnd Bergmann 2014-05-14 12:51 ` Arnd Bergmann 2014-05-14 13:07 ` Viresh Kumar 2014-05-14 13:07 ` Viresh Kumar 2014-05-14 13:16 ` Arnd Bergmann 2014-05-14 13:16 ` Arnd Bergmann 2014-05-17 0:14 ` Tomasz Figa 2014-05-17 0:14 ` Tomasz Figa 2014-05-17 0:14 ` Tomasz Figa
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