From: Marc Zyngier <marc.zyngier@arm.com> To: Abhijeet Dharmapurikar <adharmap@codeaurora.org>, Stephen Boyd <sboyd@codeaurora.org>, Phong Vo <pvo@apm.com>, Linus Walleij <linus.walleij@linaro.org>, Tin Huynh <tnhuynh@apm.com>, Y Vo <yvo@apm.com>, Thomas Gleixner <tglx@linutronix.de>, Toan Le <toanle@apm.com>, Bjorn Andersson <bjorn@kryo.se>, Jason Cooper <jason@lakedaemon.net>, Arnd Bergmann <arnd@arndb.de> Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Date: Wed, 18 Mar 2015 11:01:23 +0000 [thread overview] Message-ID: <1426676484-21812-3-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1426676484-21812-1-git-send-email-marc.zyngier@arm.com> Add the required hooks for the internal state of an interrupt to be exposed to other subsystems. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- drivers/irqchip/irq-gic.c | 69 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 471e1cd..0b4a4d0 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -151,13 +151,24 @@ static inline unsigned int gic_irq(struct irq_data *d) /* * Routines to acknowledge, disable and enable interrupts */ -static void gic_mask_irq(struct irq_data *d) +static void gic_poke_irq(struct irq_data *d, u32 offset) +{ + u32 mask = 1 << (gic_irq(d) % 32); + writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); +} + +static int gic_peek_irq(struct irq_data *d, u32 offset) { u32 mask = 1 << (gic_irq(d) % 32); + return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); +} + +static void gic_mask_irq(struct irq_data *d) +{ unsigned long flags; raw_spin_lock_irqsave(&irq_controller_lock, flags); - writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); + gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); if (gic_arch_extn.irq_mask) gic_arch_extn.irq_mask(d); raw_spin_unlock_irqrestore(&irq_controller_lock, flags); @@ -165,13 +176,12 @@ static void gic_mask_irq(struct irq_data *d) static void gic_unmask_irq(struct irq_data *d) { - u32 mask = 1 << (gic_irq(d) % 32); unsigned long flags; raw_spin_lock_irqsave(&irq_controller_lock, flags); if (gic_arch_extn.irq_unmask) gic_arch_extn.irq_unmask(d); - writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); + gic_poke_irq(d, GIC_DIST_ENABLE_SET); raw_spin_unlock_irqrestore(&irq_controller_lock, flags); } @@ -186,6 +196,55 @@ static void gic_eoi_irq(struct irq_data *d) writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); } +static int gic_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool val) +{ + u32 reg; + + switch (which) { + case IRQCHIP_STATE_PENDING: + reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; + break; + + case IRQCHIP_STATE_ACTIVE: + reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; + break; + + case IRQCHIP_STATE_MASKED: + reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; + break; + + default: + return -EINVAL; + } + + gic_poke_irq(d, reg); + return 0; +} + +static int gic_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *val) +{ + switch (which) { + case IRQCHIP_STATE_PENDING: + *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); + break; + + case IRQCHIP_STATE_ACTIVE: + *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); + break; + + case IRQCHIP_STATE_MASKED: + *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); + break; + + default: + return -EINVAL; + } + + return 0; +} + static int gic_set_type(struct irq_data *d, unsigned int type) { void __iomem *base = gic_dist_base(d); @@ -329,6 +388,8 @@ static struct irq_chip gic_chip = { .irq_set_affinity = gic_set_affinity, #endif .irq_set_wake = gic_set_wake, + .irq_get_irqchip_state = gic_irq_get_irqchip_state, + .irq_set_irqchip_state = gic_irq_set_irqchip_state, }; void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) -- 2.1.4
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Date: Wed, 18 Mar 2015 11:01:23 +0000 [thread overview] Message-ID: <1426676484-21812-3-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1426676484-21812-1-git-send-email-marc.zyngier@arm.com> Add the required hooks for the internal state of an interrupt to be exposed to other subsystems. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- drivers/irqchip/irq-gic.c | 69 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 471e1cd..0b4a4d0 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -151,13 +151,24 @@ static inline unsigned int gic_irq(struct irq_data *d) /* * Routines to acknowledge, disable and enable interrupts */ -static void gic_mask_irq(struct irq_data *d) +static void gic_poke_irq(struct irq_data *d, u32 offset) +{ + u32 mask = 1 << (gic_irq(d) % 32); + writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); +} + +static int gic_peek_irq(struct irq_data *d, u32 offset) { u32 mask = 1 << (gic_irq(d) % 32); + return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); +} + +static void gic_mask_irq(struct irq_data *d) +{ unsigned long flags; raw_spin_lock_irqsave(&irq_controller_lock, flags); - writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); + gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); if (gic_arch_extn.irq_mask) gic_arch_extn.irq_mask(d); raw_spin_unlock_irqrestore(&irq_controller_lock, flags); @@ -165,13 +176,12 @@ static void gic_mask_irq(struct irq_data *d) static void gic_unmask_irq(struct irq_data *d) { - u32 mask = 1 << (gic_irq(d) % 32); unsigned long flags; raw_spin_lock_irqsave(&irq_controller_lock, flags); if (gic_arch_extn.irq_unmask) gic_arch_extn.irq_unmask(d); - writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); + gic_poke_irq(d, GIC_DIST_ENABLE_SET); raw_spin_unlock_irqrestore(&irq_controller_lock, flags); } @@ -186,6 +196,55 @@ static void gic_eoi_irq(struct irq_data *d) writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); } +static int gic_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool val) +{ + u32 reg; + + switch (which) { + case IRQCHIP_STATE_PENDING: + reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; + break; + + case IRQCHIP_STATE_ACTIVE: + reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; + break; + + case IRQCHIP_STATE_MASKED: + reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; + break; + + default: + return -EINVAL; + } + + gic_poke_irq(d, reg); + return 0; +} + +static int gic_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *val) +{ + switch (which) { + case IRQCHIP_STATE_PENDING: + *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); + break; + + case IRQCHIP_STATE_ACTIVE: + *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); + break; + + case IRQCHIP_STATE_MASKED: + *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); + break; + + default: + return -EINVAL; + } + + return 0; +} + static int gic_set_type(struct irq_data *d, unsigned int type) { void __iomem *base = gic_dist_base(d); @@ -329,6 +388,8 @@ static struct irq_chip gic_chip = { .irq_set_affinity = gic_set_affinity, #endif .irq_set_wake = gic_set_wake, + .irq_get_irqchip_state = gic_irq_get_irqchip_state, + .irq_set_irqchip_state = gic_irq_set_irqchip_state, }; void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) -- 2.1.4
next prev parent reply other threads:[~2015-03-18 11:01 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-03-18 11:01 [PATCH v4 0/3] genirq: Saving/restoring the irqchip state of an irq line Marc Zyngier 2015-03-18 11:01 ` Marc Zyngier 2015-03-18 11:01 ` [PATCH v4 1/3] genirq: Allow the irqchip state of an IRQ to be save/restored Marc Zyngier 2015-03-18 11:01 ` Marc Zyngier 2015-04-08 17:48 ` Bjorn Andersson 2015-04-08 17:48 ` Bjorn Andersson 2015-04-08 17:48 ` Bjorn Andersson 2015-04-13 16:18 ` Srinivas Kandagatla 2015-04-13 16:18 ` Srinivas Kandagatla 2015-04-13 16:18 ` Srinivas Kandagatla 2015-04-13 16:21 ` Marc Zyngier 2015-04-13 16:21 ` Marc Zyngier 2015-04-13 16:21 ` Marc Zyngier 2015-04-08 21:30 ` [tip:irq/core] " tip-bot for Marc Zyngier 2015-03-18 11:01 ` Marc Zyngier [this message] 2015-03-18 11:01 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Marc Zyngier 2015-04-08 21:31 ` [tip:irq/core] irqchip: GIC: Add support for irq_[get, set] _irqchip_state() tip-bot for Marc Zyngier 2015-05-13 2:25 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Feng Kan 2015-05-13 2:25 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Feng Kan 2015-05-13 2:25 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Feng Kan 2015-05-13 11:58 ` Linus Walleij 2015-05-13 11:58 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Linus Walleij 2015-05-13 11:58 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Linus Walleij 2015-05-13 15:44 ` Feng Kan 2015-05-13 15:44 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Feng Kan 2015-05-13 15:44 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Feng Kan 2015-05-14 10:32 ` Linus Walleij 2015-05-14 10:32 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Linus Walleij 2015-05-14 10:32 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Linus Walleij 2015-05-14 20:14 ` Feng Kan 2015-05-14 20:14 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Feng Kan 2015-05-14 20:14 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Feng Kan 2015-05-19 8:40 ` Linus Walleij 2015-05-19 8:40 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Linus Walleij 2015-05-19 8:40 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Linus Walleij 2015-05-19 10:01 ` Marc Zyngier 2015-05-19 10:01 ` Marc Zyngier 2015-05-19 10:01 ` Marc Zyngier 2015-05-19 15:01 ` Linus Walleij 2015-05-19 15:01 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Linus Walleij 2015-05-19 15:01 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Linus Walleij 2015-05-19 21:45 ` Feng Kan 2015-05-19 21:45 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get, set}_irqchip_state Feng Kan 2015-05-19 21:45 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Feng Kan 2015-05-20 7:58 ` Marc Zyngier 2015-05-20 7:58 ` Marc Zyngier 2015-05-20 7:58 ` Marc Zyngier 2015-03-18 11:01 ` [PATCH v4 3/3] irqchip: GICv3: " Marc Zyngier 2015-03-18 11:01 ` [PATCH v4 3/3] irqchip: GICv3: Add support for irq_{get, set}_irqchip_state Marc Zyngier 2015-04-08 21:31 ` [tip:irq/core] irqchip: GICv3: Add support for irq_[get, set] _irqchip_state() tip-bot for Marc Zyngier 2015-04-13 14:12 ` [PATCH v4 0/3] genirq: Saving/restoring the irqchip state of an irq line Eric Auger 2015-04-13 14:12 ` Eric Auger
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