From: Rajendra Nayak <rnayak@codeaurora.org> To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, georgi.djakov@linaro.org, svarbanov@mm-sol.com, srinivas.kandagatla@linaro.org, sviau@codeaurora.org, Rajendra Nayak <rnayak@codeaurora.org> Subject: [PATCH v8 03/13] clk: qcom: gdsc: Add support for Memory RET/OFF Date: Thu, 6 Aug 2015 16:07:44 +0530 [thread overview] Message-ID: <1438857474-20262-4-git-send-email-rnayak@codeaurora.org> (raw) In-Reply-To: <1438857474-20262-1-git-send-email-rnayak@codeaurora.org> Along with the GDSC power switch, there is additional control to either retain all memory (core and peripheral) within a given powerdomain or to turn them off while the GDSC is powered down. Add support for these by modelling a RET state where all memory is retained and an OFF state where all memory gets turned off. The controls provided are granular enough to be able to support various differnt levels of RET states, like a 'shallow RET' with all memory retained and a 'deep RET' with some memory retained while some others are lost. The current patch does not support this and considers just one RET state where all memory is retained. Futher work, if needed can support multiple different levels of RET state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> --- drivers/clk/qcom/gdsc.c | 33 +++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 13 +++++++++++++ 2 files changed, 46 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 469b4c4..e6bbb76 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -34,6 +34,9 @@ #define EN_FEW_WAIT_VAL (0x8 << 16) #define CLK_DIS_WAIT_VAL (0x2 << 12) +#define RETAIN_MEM BIT(14) +#define RETAIN_PERIPH BIT(13) + #define TIMEOUT_US 100 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) @@ -81,6 +84,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en) return -ETIMEDOUT; } +static inline void gdsc_force_mem_on(struct gdsc *sc) +{ + int i; + u32 mask = RETAIN_MEM | RETAIN_PERIPH; + + for (i = 0; i < sc->cxc_count; i++) + regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask); +} + +static inline void gdsc_clear_mem_on(struct gdsc *sc) +{ + int i; + u32 mask = RETAIN_MEM | RETAIN_PERIPH; + + for (i = 0; i < sc->cxc_count; i++) + regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0); +} + static int gdsc_enable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); @@ -89,6 +110,10 @@ static int gdsc_enable(struct generic_pm_domain *domain) ret = gdsc_toggle_logic(sc, true); if (ret) return ret; + + if (sc->pwrsts & PWRSTS_OFF) + gdsc_force_mem_on(sc); + /* * If clocks to this power domain were already on, they will take an * additional 4 clock cycles to re-enable after the power domain is @@ -105,6 +130,9 @@ static int gdsc_disable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); + if (sc->pwrsts & PWRSTS_OFF) + gdsc_clear_mem_on(sc); + return gdsc_toggle_logic(sc, false); } @@ -129,6 +157,11 @@ static int gdsc_init(struct gdsc *sc) if (on < 0) return on; + if (on || (sc->pwrsts & PWRSTS_RET)) + gdsc_force_mem_on(sc); + else + gdsc_clear_mem_on(sc); + sc->pd.power_off = gdsc_disable; sc->pd.power_on = gdsc_enable; pm_genpd_init(&sc->pd, NULL, !on); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index f578a0c..0ff251a 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -19,16 +19,29 @@ struct regmap; +/* Powerdomain allowable state bitfields */ +#define PWRSTS_OFF BIT(0) +#define PWRSTS_RET BIT(1) +#define PWRSTS_ON BIT(2) +#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) +#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) + /** * struct gdsc - Globally Distributed Switch Controller * @pd: generic power domain * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register + * @cxcs: offsets of branch registers to toggle mem/periph bits in + * @cxc_count: number of @cxcs + * @pwrsts: Possible powerdomain power states */ struct gdsc { struct generic_pm_domain pd; struct regmap *regmap; unsigned int gdscr; + unsigned int *cxcs; + unsigned int cxc_count; + const u8 pwrsts; }; #ifdef CONFIG_QCOM_GDSC -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: rnayak@codeaurora.org (Rajendra Nayak) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 03/13] clk: qcom: gdsc: Add support for Memory RET/OFF Date: Thu, 6 Aug 2015 16:07:44 +0530 [thread overview] Message-ID: <1438857474-20262-4-git-send-email-rnayak@codeaurora.org> (raw) In-Reply-To: <1438857474-20262-1-git-send-email-rnayak@codeaurora.org> Along with the GDSC power switch, there is additional control to either retain all memory (core and peripheral) within a given powerdomain or to turn them off while the GDSC is powered down. Add support for these by modelling a RET state where all memory is retained and an OFF state where all memory gets turned off. The controls provided are granular enough to be able to support various differnt levels of RET states, like a 'shallow RET' with all memory retained and a 'deep RET' with some memory retained while some others are lost. The current patch does not support this and considers just one RET state where all memory is retained. Futher work, if needed can support multiple different levels of RET state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> --- drivers/clk/qcom/gdsc.c | 33 +++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 13 +++++++++++++ 2 files changed, 46 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 469b4c4..e6bbb76 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -34,6 +34,9 @@ #define EN_FEW_WAIT_VAL (0x8 << 16) #define CLK_DIS_WAIT_VAL (0x2 << 12) +#define RETAIN_MEM BIT(14) +#define RETAIN_PERIPH BIT(13) + #define TIMEOUT_US 100 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) @@ -81,6 +84,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en) return -ETIMEDOUT; } +static inline void gdsc_force_mem_on(struct gdsc *sc) +{ + int i; + u32 mask = RETAIN_MEM | RETAIN_PERIPH; + + for (i = 0; i < sc->cxc_count; i++) + regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask); +} + +static inline void gdsc_clear_mem_on(struct gdsc *sc) +{ + int i; + u32 mask = RETAIN_MEM | RETAIN_PERIPH; + + for (i = 0; i < sc->cxc_count; i++) + regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0); +} + static int gdsc_enable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); @@ -89,6 +110,10 @@ static int gdsc_enable(struct generic_pm_domain *domain) ret = gdsc_toggle_logic(sc, true); if (ret) return ret; + + if (sc->pwrsts & PWRSTS_OFF) + gdsc_force_mem_on(sc); + /* * If clocks to this power domain were already on, they will take an * additional 4 clock cycles to re-enable after the power domain is @@ -105,6 +130,9 @@ static int gdsc_disable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); + if (sc->pwrsts & PWRSTS_OFF) + gdsc_clear_mem_on(sc); + return gdsc_toggle_logic(sc, false); } @@ -129,6 +157,11 @@ static int gdsc_init(struct gdsc *sc) if (on < 0) return on; + if (on || (sc->pwrsts & PWRSTS_RET)) + gdsc_force_mem_on(sc); + else + gdsc_clear_mem_on(sc); + sc->pd.power_off = gdsc_disable; sc->pd.power_on = gdsc_enable; pm_genpd_init(&sc->pd, NULL, !on); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index f578a0c..0ff251a 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -19,16 +19,29 @@ struct regmap; +/* Powerdomain allowable state bitfields */ +#define PWRSTS_OFF BIT(0) +#define PWRSTS_RET BIT(1) +#define PWRSTS_ON BIT(2) +#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) +#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) + /** * struct gdsc - Globally Distributed Switch Controller * @pd: generic power domain * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register + * @cxcs: offsets of branch registers to toggle mem/periph bits in + * @cxc_count: number of @cxcs + * @pwrsts: Possible powerdomain power states */ struct gdsc { struct generic_pm_domain pd; struct regmap *regmap; unsigned int gdscr; + unsigned int *cxcs; + unsigned int cxc_count; + const u8 pwrsts; }; #ifdef CONFIG_QCOM_GDSC -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2015-08-06 10:39 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-08-06 10:37 [PATCH v8 00/13] qcom: Add support for GDSCs Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-06 10:37 ` [PATCH v8 01/13] clk: " Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 6:59 ` Stephen Boyd 2015-08-11 6:59 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 02/13] clk: qcom: gdsc: Prepare common clk probe to register gdscs Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 6:59 ` Stephen Boyd 2015-08-11 6:59 ` Stephen Boyd 2015-08-06 10:37 ` Rajendra Nayak [this message] 2015-08-06 10:37 ` [PATCH v8 03/13] clk: qcom: gdsc: Add support for Memory RET/OFF Rajendra Nayak 2015-08-11 6:59 ` Stephen Boyd 2015-08-11 6:59 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 04/13] clk: qcom: gdsc: Add support for ON only state Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 6:59 ` Stephen Boyd 2015-08-11 6:59 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 05/13] clk: qcom: gdsc: Add GDSCs in msm8916 GCC Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 6:59 ` Stephen Boyd 2015-08-11 6:59 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 06/13] clk: qcom: gdsc: Add GDSCs in msm8974 GCC Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 6:59 ` Stephen Boyd 2015-08-11 6:59 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 07/13] clk: qcom: gdsc: Add GDSCs in msm8974 MMCC Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 6:59 ` Stephen Boyd 2015-08-11 6:59 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 08/13] clk: qcom: gdsc: Add GDSCs in apq8084 GCC Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 7:01 ` Stephen Boyd 2015-08-11 7:01 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 09/13] clk: qcom: gdsc: Add GDSCs in apq8084 MMCC Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 7:02 ` Stephen Boyd 2015-08-11 7:02 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 10/13] arm: dts: qcom: Add #power-domain-cells property Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 6:53 ` Stephen Boyd 2015-08-11 6:53 ` Stephen Boyd 2015-08-13 4:24 ` Rajendra Nayak 2015-08-13 4:24 ` Rajendra Nayak 2015-08-14 1:44 ` Stephen Boyd 2015-08-14 1:44 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 11/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-11 6:52 ` Stephen Boyd 2015-08-11 6:52 ` Stephen Boyd 2015-08-13 4:23 ` Rajendra Nayak 2015-08-13 4:23 ` Rajendra Nayak 2015-11-27 8:29 ` Rajendra Nayak 2015-11-27 8:29 ` Rajendra Nayak 2015-12-01 8:59 ` Stephen Boyd 2015-12-01 8:59 ` Stephen Boyd 2015-08-06 10:37 ` [PATCH v8 12/13] clk: qcom: gdsc: Enable an RCG before turing on the gdsc Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak 2015-08-06 10:37 ` [PATCH v8 13/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM Rajendra Nayak 2015-08-06 10:37 ` Rajendra Nayak
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1438857474-20262-4-git-send-email-rnayak@codeaurora.org \ --to=rnayak@codeaurora.org \ --cc=georgi.djakov@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-pm@vger.kernel.org \ --cc=mturquette@baylibre.com \ --cc=sboyd@codeaurora.org \ --cc=srinivas.kandagatla@linaro.org \ --cc=svarbanov@mm-sol.com \ --cc=sviau@codeaurora.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.