From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/4] drm/i915/bdw: Add missing delay during L3 SQC credit programming
Date: Mon, 25 Apr 2016 15:38:05 +0300 [thread overview]
Message-ID: <1461587888-5047-1-git-send-email-imre.deak@intel.com> (raw)
BSpec requires us to wait ~100 clocks before re-enabling clock gating,
so make sure we do this.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 702f683..a6fd4dd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6711,6 +6711,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
misccpctl = I915_READ(GEN7_MISCCPCTL);
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+ /*
+ * Wait at least 100 clocks before re-enabling clock gating. See
+ * the definition of L3SQCREG1 in BSpec.
+ */
+ POSTING_READ(GEN8_L3SQCREG1);
+ udelay(1);
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
/*
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2016-04-25 12:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-25 12:38 Imre Deak [this message]
2016-04-25 12:38 ` [PATCH 2/4] drm/i915: Clean up L3 SQC register field definitions Imre Deak
2016-04-26 8:11 ` Mika Kuoppala
2016-04-26 9:03 ` Imre Deak
2016-04-26 9:21 ` Imre Deak
2016-04-26 16:55 ` Ville Syrjälä
2016-04-25 12:38 ` [PATCH 3/4] drm/i915/chv: Tune L3 SQC credits based on actual latencies Imre Deak
2016-04-25 13:16 ` Ville Syrjälä
2016-04-26 16:19 ` Ville Syrjälä
2016-04-26 16:39 ` [PATCH v2 " Imre Deak
2016-04-26 16:51 ` Ville Syrjälä
2016-04-25 12:38 ` [PATCH 4/4] drm/i915/bxt: " Imre Deak
2016-04-26 16:41 ` [PATCH v2 " Imre Deak
2016-04-26 16:53 ` Ville Syrjälä
2016-04-25 14:03 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/bdw: Add missing delay during L3 SQC credit programming Patchwork
2016-04-26 16:55 ` [PATCH 1/4] " Ville Syrjälä
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1461587888-5047-1-git-send-email-imre.deak@intel.com \
--to=imre.deak@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.