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From: Andre Przywara <andre.przywara@arm.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
	Christoffer Dall <christoffer.dall@linaro.org>
Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 09/57] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr
Date: Thu, 19 May 2016 19:07:48 +0100	[thread overview]
Message-ID: <1463681316-23039-10-git-send-email-andre.przywara@arm.com> (raw)
In-Reply-To: <1463681316-23039-1-git-send-email-andre.przywara@arm.com>

From: Christoffer Dall <christoffer.dall@linaro.org>

The number of list registers is a property of the underlying system, not
of emulated VGIC CPU interface.

As we are about to move this variable to global state in the new vgic
for clarity, move it from the legacy implementation as well to make the
merge of the new code easier.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
 include/kvm/arm_vgic.h        |  3 ---
 virt/kvm/arm/hyp/vgic-v2-sr.c | 12 +++++++-----
 virt/kvm/arm/vgic-v2.c        |  4 +++-
 virt/kvm/arm/vgic.c           | 12 ++----------
 4 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index 3e17fb4..67a6637 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -304,9 +304,6 @@ struct vgic_cpu {
 	unsigned long   *active_shared;
 	unsigned long   *pend_act_shared;
 
-	/* Number of list registers on this CPU */
-	int		nr_lr;
-
 	/* CPU vif control registers for world switch */
 	union {
 		struct vgic_v2_cpu_if	vgic_v2;
diff --git a/virt/kvm/arm/hyp/vgic-v2-sr.c b/virt/kvm/arm/hyp/vgic-v2-sr.c
index 674bdf8..caac41f 100644
--- a/virt/kvm/arm/hyp/vgic-v2-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v2-sr.c
@@ -21,11 +21,13 @@
 
 #include <asm/kvm_hyp.h>
 
+extern struct vgic_params vgic_v2_params;
+
 static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
 					    void __iomem *base)
 {
 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
-	int nr_lr = vcpu->arch.vgic_cpu.nr_lr;
+	int nr_lr = (kern_hyp_va(&vgic_v2_params))->nr_lr;
 	u32 eisr0, eisr1;
 	int i;
 	bool expect_mi;
@@ -67,7 +69,7 @@ static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
 static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
 {
 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
-	int nr_lr = vcpu->arch.vgic_cpu.nr_lr;
+	int nr_lr = (kern_hyp_va(&vgic_v2_params))->nr_lr;
 	u32 elrsr0, elrsr1;
 
 	elrsr0 = readl_relaxed(base + GICH_ELRSR0);
@@ -86,7 +88,7 @@ static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
 static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
 {
 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
-	int nr_lr = vcpu->arch.vgic_cpu.nr_lr;
+	int nr_lr = (kern_hyp_va(&vgic_v2_params))->nr_lr;
 	int i;
 
 	for (i = 0; i < nr_lr; i++) {
@@ -141,13 +143,13 @@ void __hyp_text __vgic_v2_restore_state(struct kvm_vcpu *vcpu)
 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 	struct vgic_dist *vgic = &kvm->arch.vgic;
 	void __iomem *base = kern_hyp_va(vgic->vctrl_base);
-	int i, nr_lr;
+	int nr_lr = (kern_hyp_va(&vgic_v2_params))->nr_lr;
+	int i;
 	u64 live_lrs = 0;
 
 	if (!base)
 		return;
 
-	nr_lr = vcpu->arch.vgic_cpu.nr_lr;
 
 	for (i = 0; i < nr_lr; i++)
 		if (cpu_if->vgic_lr[i] & GICH_LR_STATE)
diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c
index 7e826c9..334cd7a 100644
--- a/virt/kvm/arm/vgic-v2.c
+++ b/virt/kvm/arm/vgic-v2.c
@@ -171,7 +171,7 @@ static const struct vgic_ops vgic_v2_ops = {
 	.enable			= vgic_v2_enable,
 };
 
-static struct vgic_params vgic_v2_params;
+struct vgic_params __section(.hyp.text) vgic_v2_params;
 
 static void vgic_cpu_init_lrs(void *params)
 {
@@ -201,6 +201,8 @@ int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info,
 	const struct resource *vctrl_res = &gic_kvm_info->vctrl;
 	const struct resource *vcpu_res = &gic_kvm_info->vcpu;
 
+	memset(vgic, 0, sizeof(*vgic));
+
 	if (!gic_kvm_info->maint_irq) {
 		kvm_err("error getting vgic maintenance irq\n");
 		ret = -ENXIO;
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 91d42a8..f76bb64 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -690,12 +690,11 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio,
  */
 void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
 {
-	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 	u64 elrsr = vgic_get_elrsr(vcpu);
 	unsigned long *elrsr_ptr = u64_to_bitmask(&elrsr);
 	int i;
 
-	for_each_clear_bit(i, elrsr_ptr, vgic_cpu->nr_lr) {
+	for_each_clear_bit(i, elrsr_ptr, vgic->nr_lr) {
 		struct vgic_lr lr = vgic_get_lr(vcpu, i);
 
 		/*
@@ -1106,7 +1105,7 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq)
 {
 	int i;
 
-	for (i = 0; i < vcpu->arch.vgic_cpu.nr_lr; i++) {
+	for (i = 0; i < vgic->nr_lr; i++) {
 		struct vgic_lr vlr = vgic_get_lr(vcpu, i);
 
 		if (vlr.irq == virt_irq && vlr.state & LR_STATE_ACTIVE)
@@ -1866,13 +1865,6 @@ static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs)
 		return -ENOMEM;
 	}
 
-	/*
-	 * Store the number of LRs per vcpu, so we don't have to go
-	 * all the way to the distributor structure to find out. Only
-	 * assembly code should use this one.
-	 */
-	vgic_cpu->nr_lr = vgic->nr_lr;
-
 	return 0;
 }
 
-- 
2.8.2

WARNING: multiple messages have this Message-ID (diff)
From: andre.przywara@arm.com (Andre Przywara)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 09/57] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr
Date: Thu, 19 May 2016 19:07:48 +0100	[thread overview]
Message-ID: <1463681316-23039-10-git-send-email-andre.przywara@arm.com> (raw)
In-Reply-To: <1463681316-23039-1-git-send-email-andre.przywara@arm.com>

From: Christoffer Dall <christoffer.dall@linaro.org>

The number of list registers is a property of the underlying system, not
of emulated VGIC CPU interface.

As we are about to move this variable to global state in the new vgic
for clarity, move it from the legacy implementation as well to make the
merge of the new code easier.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
 include/kvm/arm_vgic.h        |  3 ---
 virt/kvm/arm/hyp/vgic-v2-sr.c | 12 +++++++-----
 virt/kvm/arm/vgic-v2.c        |  4 +++-
 virt/kvm/arm/vgic.c           | 12 ++----------
 4 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index 3e17fb4..67a6637 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -304,9 +304,6 @@ struct vgic_cpu {
 	unsigned long   *active_shared;
 	unsigned long   *pend_act_shared;
 
-	/* Number of list registers on this CPU */
-	int		nr_lr;
-
 	/* CPU vif control registers for world switch */
 	union {
 		struct vgic_v2_cpu_if	vgic_v2;
diff --git a/virt/kvm/arm/hyp/vgic-v2-sr.c b/virt/kvm/arm/hyp/vgic-v2-sr.c
index 674bdf8..caac41f 100644
--- a/virt/kvm/arm/hyp/vgic-v2-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v2-sr.c
@@ -21,11 +21,13 @@
 
 #include <asm/kvm_hyp.h>
 
+extern struct vgic_params vgic_v2_params;
+
 static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
 					    void __iomem *base)
 {
 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
-	int nr_lr = vcpu->arch.vgic_cpu.nr_lr;
+	int nr_lr = (kern_hyp_va(&vgic_v2_params))->nr_lr;
 	u32 eisr0, eisr1;
 	int i;
 	bool expect_mi;
@@ -67,7 +69,7 @@ static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
 static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
 {
 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
-	int nr_lr = vcpu->arch.vgic_cpu.nr_lr;
+	int nr_lr = (kern_hyp_va(&vgic_v2_params))->nr_lr;
 	u32 elrsr0, elrsr1;
 
 	elrsr0 = readl_relaxed(base + GICH_ELRSR0);
@@ -86,7 +88,7 @@ static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
 static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
 {
 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
-	int nr_lr = vcpu->arch.vgic_cpu.nr_lr;
+	int nr_lr = (kern_hyp_va(&vgic_v2_params))->nr_lr;
 	int i;
 
 	for (i = 0; i < nr_lr; i++) {
@@ -141,13 +143,13 @@ void __hyp_text __vgic_v2_restore_state(struct kvm_vcpu *vcpu)
 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 	struct vgic_dist *vgic = &kvm->arch.vgic;
 	void __iomem *base = kern_hyp_va(vgic->vctrl_base);
-	int i, nr_lr;
+	int nr_lr = (kern_hyp_va(&vgic_v2_params))->nr_lr;
+	int i;
 	u64 live_lrs = 0;
 
 	if (!base)
 		return;
 
-	nr_lr = vcpu->arch.vgic_cpu.nr_lr;
 
 	for (i = 0; i < nr_lr; i++)
 		if (cpu_if->vgic_lr[i] & GICH_LR_STATE)
diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c
index 7e826c9..334cd7a 100644
--- a/virt/kvm/arm/vgic-v2.c
+++ b/virt/kvm/arm/vgic-v2.c
@@ -171,7 +171,7 @@ static const struct vgic_ops vgic_v2_ops = {
 	.enable			= vgic_v2_enable,
 };
 
-static struct vgic_params vgic_v2_params;
+struct vgic_params __section(.hyp.text) vgic_v2_params;
 
 static void vgic_cpu_init_lrs(void *params)
 {
@@ -201,6 +201,8 @@ int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info,
 	const struct resource *vctrl_res = &gic_kvm_info->vctrl;
 	const struct resource *vcpu_res = &gic_kvm_info->vcpu;
 
+	memset(vgic, 0, sizeof(*vgic));
+
 	if (!gic_kvm_info->maint_irq) {
 		kvm_err("error getting vgic maintenance irq\n");
 		ret = -ENXIO;
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 91d42a8..f76bb64 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -690,12 +690,11 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio,
  */
 void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
 {
-	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 	u64 elrsr = vgic_get_elrsr(vcpu);
 	unsigned long *elrsr_ptr = u64_to_bitmask(&elrsr);
 	int i;
 
-	for_each_clear_bit(i, elrsr_ptr, vgic_cpu->nr_lr) {
+	for_each_clear_bit(i, elrsr_ptr, vgic->nr_lr) {
 		struct vgic_lr lr = vgic_get_lr(vcpu, i);
 
 		/*
@@ -1106,7 +1105,7 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq)
 {
 	int i;
 
-	for (i = 0; i < vcpu->arch.vgic_cpu.nr_lr; i++) {
+	for (i = 0; i < vgic->nr_lr; i++) {
 		struct vgic_lr vlr = vgic_get_lr(vcpu, i);
 
 		if (vlr.irq == virt_irq && vlr.state & LR_STATE_ACTIVE)
@@ -1866,13 +1865,6 @@ static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs)
 		return -ENOMEM;
 	}
 
-	/*
-	 * Store the number of LRs per vcpu, so we don't have to go
-	 * all the way to the distributor structure to find out. Only
-	 * assembly code should use this one.
-	 */
-	vgic_cpu->nr_lr = vgic->nr_lr;
-
 	return 0;
 }
 
-- 
2.8.2

  parent reply	other threads:[~2016-05-19 18:07 UTC|newest]

Thread overview: 118+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-19 18:07 [PATCH v5 00/57] KVM: arm/arm64: Rework virtual GIC emulation Andre Przywara
2016-05-19 18:07 ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 01/57] KVM: arm/arm64: vgic: streamline vgic_update_irq_pending() interface Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 02/57] KVM: arm/arm64: vgic: avoid map in kvm_vgic_inject_mapped_irq() Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 03/57] KVM: arm/arm64: vgic: avoid map in kvm_vgic_map_is_active() Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 04/57] KVM: arm/arm64: vgic: avoid map in kvm_vgic_unmap_phys_irq() Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 05/57] KVM: arm/arm64: Remove the IRQ field from struct irq_phys_map Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 06/57] KVM: arm/arm64: arch_timer: Remove irq_phys_map Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 07/57] KVM: arm/arm64: vgic: Remove irq_phys_map from interface Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 08/57] KVM: arm/arm64: Move timer IRQ map to latest possible time Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` Andre Przywara [this message]
2016-05-19 18:07   ` [PATCH v5 09/57] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr Andre Przywara
2016-05-19 18:07 ` [PATCH v5 10/57] KVM: arm/arm64: Fix MMIO emulation data handling Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 11/57] KVM: arm/arm64: Export mmio_read/write_bus Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 12/57] KVM: arm/arm64: pmu: abstract access to number of SPIs Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 13/57] KVM: arm/arm64: Provide functionality to pause and resume a guest Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 14/57] KVM: arm/arm64: move GICv2 emulation defines into arm-gic-v3.h Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 15/57] KVM: arm/arm64: vgic-new: Add data structure definitions Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 16/57] KVM: arm/arm64: vgic-new: Add acccessor to new struct vgic_irq instance Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 17/57] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 18/57] KVM: arm/arm64: vgic-new: Add IRQ sorting Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 19/57] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 20/57] KVM: arm/arm64: vgic-new: Add GICv2 world switch backend Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 21/57] KVM: arm/arm64: vgic-new: Add GICv3 " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 22/57] KVM: arm/arm64: vgic-new: Implement kvm_vgic_vcpu_pending_irq Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 23/57] KVM: arm/arm64: vgic-new: Add MMIO handling framework Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 24/57] KVM: arm/arm64: vgic-new: Add GICv2 " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 25/57] KVM: arm/arm64: vgic-new: Add CTLR, TYPER and IIDR handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 26/57] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 27/57] KVM: arm/arm64: vgic-new: Add PENDING " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 28/57] KVM: arm/arm64: vgic-new: Add ACTIVE " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 29/57] KVM: arm/arm64: vgic-new: Add PRIORITY " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 30/57] KVM: arm/arm64: vgic-new: Add CONFIG " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 31/57] KVM: arm/arm64: vgic-new: Add TARGET " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 32/57] KVM: arm/arm64: vgic-new: Add SGIR register handler Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 33/57] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 34/57] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 35/57] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 36/57] KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 37/57] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 38/57] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 39/57] KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 40/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM device ops registration Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 41/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_NR_IRQS Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 42/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_CTRL Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 43/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: implement kvm_vgic_addr Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 44/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_ADDR Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 45/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: access to VGIC registers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 46/57] KVM: arm/arm64: vgic-new: Export register access interface Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 47/57] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 48/57] KVM: arm/arm64: vgic-new: Add GICH_VMCR accessors Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 49/57] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 50/57] KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 51/57] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_create Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 52/57] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 53/57] KVM: arm/arm64: vgic-new: vgic_init: implement map_resources Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 54/57] KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 55/57] KVM: arm/arm64: vgic-new: Wire up irqfd injection Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 56/57] KVM: arm/arm64: vgic-new: implement mapped IRQ handling Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 57/57] KVM: arm/arm64: vgic-new: enable build Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-20 15:04 ` [PATCH v5 00/57] KVM: arm/arm64: Rework virtual GIC emulation Christoffer Dall
2016-05-20 15:04   ` Christoffer Dall

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