From: Bob Paauwe <bob.j.paauwe@intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: [PATCH] drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.
Date: Fri, 18 Nov 2016 14:11:56 -0800 [thread overview]
Message-ID: <1479507116-13224-1-git-send-email-bob.j.paauwe@intel.com> (raw)
For a single link (channel) DSI panel we want to use a larger divider
and keep the clock rate down to save power when in DPI/video mode. However
when using a dual-link DSI panel this may reduce the clock below what's
needed to get a stable display.
Use the smaller divider (faster clock) for either DBI/command mode or
when using dual link.
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..9edc57e 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -414,8 +414,13 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
- /* As per bpsec program the 8/3X clock divider to the below value */
- if (dev_priv->vbt.dsi.config->is_cmd_mode)
+ /*
+ * Set the 8/3X clock to divide by 3 for DBI mode as it needs a
+ * faster clock than DPI mode. However, dual link panels also
+ * need the faster clock, even when in DPI mode.
+ */
+ if (dev_priv->vbt.dsi.config->is_cmd_mode ||
+ dev_priv->vbt.dsi.config->dual_link)
mipi_8by3_divider = 0x2;
else
mipi_8by3_divider = 0x3;
--
2.7.4
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next reply other threads:[~2016-11-18 22:13 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-18 22:11 Bob Paauwe [this message]
2016-11-18 22:46 ` ✗ Fi.CI.BAT: warning for drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link Patchwork
2016-11-19 10:20 ` [PATCH] " David Weinehall
2016-11-21 18:06 ` Bob Paauwe
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