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From: Will Deacon <will.deacon@arm.com>
To: linux-kernel@vger.kernel.org
Cc: peterz@infradead.org, benh@au1.ibm.com,
	torvalds@linux-foundation.org, npiggin@gmail.com,
	catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org,
	Will Deacon <will.deacon@arm.com>
Subject: [RFC PATCH 02/11] arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()
Date: Fri, 24 Aug 2018 16:52:37 +0100	[thread overview]
Message-ID: <1535125966-7666-3-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1535125966-7666-1-git-send-email-will.deacon@arm.com>

__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.

In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/include/asm/tlbflush.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 7e2a35424ca4..e257f8655b84 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -213,6 +213,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
 {
 	unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm));
 
+	dsb(ishst);
 	__tlbi(vae1is, addr);
 	__tlbi_user(vae1is, addr);
 	dsb(ish);
@@ -222,6 +223,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
 {
 	unsigned long addr = __TLBI_VADDR(kaddr, 0);
 
+	dsb(ishst);
 	__tlbi(vaae1is, addr);
 	dsb(ish);
 }
-- 
2.1.4


WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 02/11] arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()
Date: Fri, 24 Aug 2018 16:52:37 +0100	[thread overview]
Message-ID: <1535125966-7666-3-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1535125966-7666-1-git-send-email-will.deacon@arm.com>

__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.

In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/include/asm/tlbflush.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 7e2a35424ca4..e257f8655b84 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -213,6 +213,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
 {
 	unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm));
 
+	dsb(ishst);
 	__tlbi(vae1is, addr);
 	__tlbi_user(vae1is, addr);
 	dsb(ish);
@@ -222,6 +223,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
 {
 	unsigned long addr = __TLBI_VADDR(kaddr, 0);
 
+	dsb(ishst);
 	__tlbi(vaae1is, addr);
 	dsb(ish);
 }
-- 
2.1.4

  parent reply	other threads:[~2018-08-24 15:52 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-24 15:52 [RFC PATCH 00/11] Avoid synchronous TLB invalidation for intermediate page-table entries on arm64 Will Deacon
2018-08-24 15:52 ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 01/11] arm64: tlb: Use last-level invalidation in flush_tlb_kernel_range() Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-24 15:52 ` Will Deacon [this message]
2018-08-24 15:52   ` [RFC PATCH 02/11] arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable() Will Deacon
2018-08-24 17:56   ` Peter Zijlstra
2018-08-24 17:56     ` Peter Zijlstra
2018-08-28 13:03     ` Will Deacon
2018-08-28 13:03       ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 03/11] arm64: pgtable: Implement p[mu]d_valid() and check in set_p[mu]d() Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-24 16:15   ` Linus Torvalds
2018-08-24 16:15     ` Linus Torvalds
2018-08-28 12:49     ` Will Deacon
2018-08-28 12:49       ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 04/11] arm64: tlb: Justify non-leaf invalidation in flush_tlb_range() Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 05/11] arm64: tlbflush: Allow stride to be specified for __flush_tlb_range() Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 06/11] arm64: tlb: Remove redundant !CONFIG_HAVE_RCU_TABLE_FREE code Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 07/11] asm-generic/tlb: Guard with #ifdef CONFIG_MMU Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 08/11] asm-generic/tlb: Track freeing of page-table directories in struct mmu_gather Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-27  4:44   ` Nicholas Piggin
2018-08-27  4:44     ` Nicholas Piggin
2018-08-28 13:46     ` Peter Zijlstra
2018-08-28 13:46       ` Peter Zijlstra
2018-08-28 13:48       ` Peter Zijlstra
2018-08-28 13:48         ` Peter Zijlstra
2018-08-28 14:12       ` Nicholas Piggin
2018-08-28 14:12         ` Nicholas Piggin
2018-08-24 15:52 ` [RFC PATCH 09/11] asm-generic/tlb: Track which levels of the page tables have been cleared Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-27  7:53   ` Peter Zijlstra
2018-08-27  7:53     ` Peter Zijlstra
2018-08-28 13:12     ` Will Deacon
2018-08-28 13:12       ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 10/11] arm64: tlb: Adjust stride and type of TLBI according to mmu_gather Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-24 15:52 ` [RFC PATCH 11/11] arm64: tlb: Avoid synchronous TLBIs when freeing page tables Will Deacon
2018-08-24 15:52   ` Will Deacon
2018-08-24 16:20 ` [RFC PATCH 00/11] Avoid synchronous TLB invalidation for intermediate page-table entries on arm64 Linus Torvalds
2018-08-24 16:20   ` Linus Torvalds
2018-08-26 10:56   ` Peter Zijlstra
2018-08-26 10:56     ` Peter Zijlstra
2018-09-04 18:38 ` Jon Masters
2018-09-04 18:38   ` Jon Masters
2018-09-05 12:28   ` Will Deacon
2018-09-05 12:28     ` Will Deacon
2018-09-07  6:36     ` Jon Masters
2018-09-07  6:36       ` Jon Masters
2018-09-13 15:53       ` Will Deacon
2018-09-13 15:53         ` Will Deacon
2018-09-13 16:53         ` Jon Masters
2018-09-13 16:53           ` Jon Masters

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