From: Sowjanya Komatineni <skomatineni@nvidia.com> To: thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, skomatineni@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com, devicetree@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-pm@vger.kernel.org Subject: [PATCH v9 17/22] soc/tegra: pmc: Add pmc wake support for tegra210 Date: Fri, 16 Aug 2019 12:42:02 -0700 [thread overview] Message-ID: <1565984527-5272-18-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1565984527-5272-1-git-send-email-skomatineni@nvidia.com> This patch implements PMC wakeup sequence for Tegra210 and defines common used RTC alarm wake event. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/soc/tegra/pmc.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 91c84d0e66ae..76e7292ded25 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -58,6 +58,11 @@ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ #define PMC_CNTRL_MAIN_RST BIT(4) +#define PMC_WAKE_MASK 0x0c +#define PMC_WAKE_LEVEL 0x10 +#define PMC_WAKE_STATUS 0x14 +#define PMC_SW_WAKE_STATUS 0x18 + #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE BIT(0) #define DPD_SAMPLE_DISABLE (0 << 0) @@ -87,6 +92,11 @@ #define PMC_SCRATCH41 0x140 +#define PMC_WAKE2_MASK 0x160 +#define PMC_WAKE2_LEVEL 0x164 +#define PMC_WAKE2_STATUS 0x168 +#define PMC_SW_WAKE2_STATUS 0x16c + #define PMC_SENSOR_CTRL 0x1b0 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) @@ -1922,6 +1932,43 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; +static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + /* clear wake status */ + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); + + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); + + /* enable PMC wake */ + if (data->hwirq >= 32) + offset = PMC_WAKE2_MASK; + else + offset = PMC_WAKE_MASK; + + value = tegra_pmc_readl(pmc, offset); + + if (on) + value |= BIT(bit); + else + value &= ~BIT(bit); + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -1954,6 +2001,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + if (data->hwirq >= 32) + offset = PMC_WAKE2_LEVEL; + else + offset = PMC_WAKE_LEVEL; + + value = tegra_pmc_readl(pmc, offset); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + value |= BIT(bit); + break; + + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + value &= ~BIT(bit); + break; + + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: + value ^= BIT(bit); + break; + + default: + return -EINVAL; + } + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -2540,6 +2630,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = { TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) }; +static const struct tegra_wake_event tegra210_wake_events[] = { + TEGRA_WAKE_IRQ("rtc", 16, 2), +}; + static const struct tegra_pmc_soc tegra210_pmc_soc = { .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, @@ -2557,10 +2651,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .irq_set_wake = tegra210_pmc_irq_set_wake, + .irq_set_type = tegra210_pmc_irq_set_type, .reset_sources = tegra210_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, + .num_wake_events = ARRAY_SIZE(tegra210_wake_events), + .wake_events = tegra210_wake_events, }; #define TEGRA186_IO_PAD_TABLE(_pad) \ -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <tglx@linutronix.de>, <jason@lakedaemon.net>, <marc.zyngier@arm.com>, <linus.walleij@linaro.org>, <stefan@agner.ch>, <mark.rutland@arm.com> Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>, <sboyd@kernel.org>, <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>, <josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>, <digetx@gmail.com>, <devicetree@vger.kernel.org>, <rjw@rjwysocki.net>, <viresh.kumar@linaro.org>, <linux-pm@vger.kernel.org> Subject: [PATCH v9 17/22] soc/tegra: pmc: Add pmc wake support for tegra210 Date: Fri, 16 Aug 2019 12:42:02 -0700 [thread overview] Message-ID: <1565984527-5272-18-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1565984527-5272-1-git-send-email-skomatineni@nvidia.com> This patch implements PMC wakeup sequence for Tegra210 and defines common used RTC alarm wake event. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/soc/tegra/pmc.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 91c84d0e66ae..76e7292ded25 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -58,6 +58,11 @@ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ #define PMC_CNTRL_MAIN_RST BIT(4) +#define PMC_WAKE_MASK 0x0c +#define PMC_WAKE_LEVEL 0x10 +#define PMC_WAKE_STATUS 0x14 +#define PMC_SW_WAKE_STATUS 0x18 + #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE BIT(0) #define DPD_SAMPLE_DISABLE (0 << 0) @@ -87,6 +92,11 @@ #define PMC_SCRATCH41 0x140 +#define PMC_WAKE2_MASK 0x160 +#define PMC_WAKE2_LEVEL 0x164 +#define PMC_WAKE2_STATUS 0x168 +#define PMC_SW_WAKE2_STATUS 0x16c + #define PMC_SENSOR_CTRL 0x1b0 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) @@ -1922,6 +1932,43 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; +static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + /* clear wake status */ + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); + + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); + + /* enable PMC wake */ + if (data->hwirq >= 32) + offset = PMC_WAKE2_MASK; + else + offset = PMC_WAKE_MASK; + + value = tegra_pmc_readl(pmc, offset); + + if (on) + value |= BIT(bit); + else + value &= ~BIT(bit); + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -1954,6 +2001,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + if (data->hwirq >= 32) + offset = PMC_WAKE2_LEVEL; + else + offset = PMC_WAKE_LEVEL; + + value = tegra_pmc_readl(pmc, offset); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + value |= BIT(bit); + break; + + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + value &= ~BIT(bit); + break; + + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: + value ^= BIT(bit); + break; + + default: + return -EINVAL; + } + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -2540,6 +2630,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = { TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) }; +static const struct tegra_wake_event tegra210_wake_events[] = { + TEGRA_WAKE_IRQ("rtc", 16, 2), +}; + static const struct tegra_pmc_soc tegra210_pmc_soc = { .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, @@ -2557,10 +2651,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .irq_set_wake = tegra210_pmc_irq_set_wake, + .irq_set_type = tegra210_pmc_irq_set_type, .reset_sources = tegra210_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, + .num_wake_events = ARRAY_SIZE(tegra210_wake_events), + .wake_events = tegra210_wake_events, }; #define TEGRA186_IO_PAD_TABLE(_pad) \ -- 2.7.4
next prev parent reply other threads:[~2019-08-16 19:42 UTC|newest] Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-16 19:41 [PATCH v9 00/22] SC7 entry and exit support for Tegra210 Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 01/22] pinctrl: tegra: Fix write barrier placement in pmx_writel Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-18 22:20 ` Linus Walleij 2019-08-18 22:20 ` Linus Walleij 2019-08-16 19:41 ` [PATCH v9 02/22] pinctrl: tegra: Flush pinctrl writes during resume Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-18 22:20 ` Linus Walleij 2019-08-18 22:20 ` Linus Walleij 2019-08-16 19:41 ` [PATCH v9 03/22] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 04/22] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 05/22] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 06/22] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 07/22] clk: Add API to get index of the clock parent Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-06 23:10 ` Stephen Boyd 2019-11-06 23:10 ` Stephen Boyd 2019-11-07 0:54 ` Dmitry Osipenko 2019-11-07 15:21 ` Thierry Reding 2019-11-07 19:19 ` Stephen Boyd 2019-11-08 10:11 ` Thierry Reding 2019-11-08 18:12 ` Stephen Boyd 2019-11-08 18:55 ` Thierry Reding 2019-11-08 21:15 ` Stephen Boyd 2019-08-16 19:41 ` [PATCH v9 08/22] clk: tegra: periph: Add restore_context support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 09/22] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 10/22] clk: tegra: clk-super: Add restore-context support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 11/22] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-08 21:20 ` Stephen Boyd 2019-11-08 21:20 ` Stephen Boyd 2019-11-08 23:38 ` Dmitry Osipenko 2019-08-16 19:41 ` [PATCH v9 12/22] cpufreq: tegra124: " Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-02 14:42 ` Thierry Reding 2019-11-02 14:42 ` Thierry Reding 2019-08-16 19:41 ` [PATCH v9 13/22] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 14/22] clk: tegra: Share clk and rst register defines with Tegra clock driver Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 15/22] clk: tegra210: Add suspend and resume support Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-19 16:47 ` Dmitry Osipenko 2019-08-16 19:42 ` [PATCH v9 16/22] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni [this message] 2019-08-16 19:42 ` [PATCH v9 17/22] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 18/22] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 19/22] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 20/22] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-19 16:48 ` Dmitry Osipenko 2019-08-19 18:20 ` Sowjanya Komatineni 2019-08-19 18:20 ` Sowjanya Komatineni 2019-08-19 19:07 ` Sowjanya Komatineni 2019-08-19 19:07 ` Sowjanya Komatineni 2019-08-19 19:33 ` Dmitry Osipenko 2019-08-16 19:42 ` [PATCH v9 21/22] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 22/22] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni
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