From: Shawn Lin <shawn.lin@rock-chips.com> To: Heiko Stuebner <heiko@sntech.de>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Rob Herring <robh+dt@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>, Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com>, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, William Wu <william.wu@rock-chips.com>, Simon Xue <xxm@rock-chips.com>, linux-rockchip@lists.infradead.org, Shawn Lin <shawn.lin@rock-chips.com> Subject: [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP Date: Tue, 14 Jan 2020 15:22:55 +0800 [thread overview] Message-ID: <1578986580-71974-2-git-send-email-shawn.lin@rock-chips.com> (raw) In-Reply-To: <1578986580-71974-1-git-send-email-shawn.lin@rock-chips.com> This IP could supports USB3.0 and PCIe. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- .../bindings/phy/rockchip,inno-combophy.yaml | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml new file mode 100644 index 0000000..d647ab3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,inno-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip USB3.0/PCI-e combo phy + +maintainers: + - Shawn Lin <shawn.lin@rock-chips.com> + - William Wu <william.wu@rock-chips.com> + +properties: + "#phy-cells": + const: 1 + + compatible: + enum: + - rockchip,rk1808-combphy + + reg: + maxItems: 1 + + clocks: + items: + - description: PLL reference clock + + clock-names: + items: + - const: refclk + + resets: + items: + - description: OTG unit reset line + - description: POR unit reset line + - description: APB interface reset line + - description: PIPE unit reset line + + reset-names: + items: + - const: otg-rst + - const: combphy-por + - const: combphy-apb + - const: combphy-pipe + + rockchip,combphygrf: + items: + - description: The grf for COMBPHY configuration and state registers. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - rockchip,combphygrf + +additionalProperties: false + +examples: + - | + combphy_grf: syscon@fe018000 { + compatible = "rockchip,usb3phy-grf", "syscon"; + reg = <0x0 0xfe018000 0x0 0x8000>; + }; + + combphy: phy@ff380000 { + compatible = "rockchip,rk1808-combphy"; + reg = <0x0 0xff380000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-rates = <25000000>; + resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, + <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>; + reset-names = "otg-rst", "combphy-por", + "combphy-apb", "combphy-pipe"; + rockchip,combphygrf = <&combphy_grf>; + }; + +... -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> To: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>, Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>, Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Simon Xue <xxm-TNX95d0MmH7DzftRWevZcw@public.gmane.org>, Jingoo Han <jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Subject: [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP Date: Tue, 14 Jan 2020 15:22:55 +0800 [thread overview] Message-ID: <1578986580-71974-2-git-send-email-shawn.lin@rock-chips.com> (raw) In-Reply-To: <1578986580-71974-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> This IP could supports USB3.0 and PCIe. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- .../bindings/phy/rockchip,inno-combophy.yaml | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml new file mode 100644 index 0000000..d647ab3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,inno-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip USB3.0/PCI-e combo phy + +maintainers: + - Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + - William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + enum: + - rockchip,rk1808-combphy + + reg: + maxItems: 1 + + clocks: + items: + - description: PLL reference clock + + clock-names: + items: + - const: refclk + + resets: + items: + - description: OTG unit reset line + - description: POR unit reset line + - description: APB interface reset line + - description: PIPE unit reset line + + reset-names: + items: + - const: otg-rst + - const: combphy-por + - const: combphy-apb + - const: combphy-pipe + + rockchip,combphygrf: + items: + - description: The grf for COMBPHY configuration and state registers. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - rockchip,combphygrf + +additionalProperties: false + +examples: + - | + combphy_grf: syscon@fe018000 { + compatible = "rockchip,usb3phy-grf", "syscon"; + reg = <0x0 0xfe018000 0x0 0x8000>; + }; + + combphy: phy@ff380000 { + compatible = "rockchip,rk1808-combphy"; + reg = <0x0 0xff380000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-rates = <25000000>; + resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, + <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>; + reset-names = "otg-rst", "combphy-por", + "combphy-apb", "combphy-pipe"; + rockchip,combphygrf = <&combphy_grf>; + }; + +... -- 1.9.1
next prev parent reply other threads:[~2020-01-14 7:23 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-01-14 7:22 [PATCH 0/6] Add Rockchip new PCIe controller and combo phy support Shawn Lin 2020-01-14 7:22 ` Shawn Lin 2020-01-14 7:22 ` Shawn Lin [this message] 2020-01-14 7:22 ` [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP Shawn Lin 2020-01-14 23:43 ` Rob Herring 2020-01-14 23:43 ` Rob Herring 2020-01-16 0:03 ` [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP【请注意,邮件由linux-rockchip-bounces+shawn.lin=rock-chips.com@lists.infradead.org代发】 Shawn Lin 2020-01-16 0:03 ` Shawn Lin 2020-01-14 7:22 ` [PATCH 2/6] phy/rockchip: inno-combophy: Add initial support Shawn Lin 2020-01-14 7:22 ` Shawn Lin 2020-01-14 7:22 ` [PATCH 3/6] PCI: dwc: Skip allocating own MSI domain if using external MSI domain Shawn Lin 2020-01-14 7:22 ` Shawn Lin 2020-01-14 7:22 ` [PATCH 4/6] dt-bindings: rockchip: Add DesignWare based PCIe controller Shawn Lin 2020-01-14 7:22 ` Shawn Lin 2020-01-15 0:05 ` Rob Herring 2020-01-14 7:25 ` [PATCH 5/6] PCI: rockchip: add " Shawn Lin 2020-01-14 7:25 ` Shawn Lin 2020-01-15 17:24 ` Bjorn Helgaas 2020-01-16 0:14 ` Shawn Lin 2020-01-16 0:14 ` Shawn Lin 2020-01-16 21:36 ` Jingoo Han 2020-01-16 21:36 ` Jingoo Han 2020-01-18 16:36 ` Francesco Lavra 2020-01-18 16:36 ` Francesco Lavra 2020-01-20 0:55 ` Shawn Lin 2020-01-20 0:55 ` Shawn Lin 2020-01-14 7:25 ` [PATCH 6/6] MAINTAINERS: Update PCIe drivers for Rockchip Shawn Lin 2020-01-14 7:25 ` Shawn Lin
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