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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org,
	mark.rutland@arm.com, suzuki.poulose@arm.com,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH V4 17/17] arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context
Date: Tue, 19 May 2020 15:10:54 +0530	[thread overview]
Message-ID: <1589881254-10082-18-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1589881254-10082-1-git-send-email-anshuman.khandual@arm.com>

ID_MMFR4_EL1 has been missing in the CPU context (i.e cpuinfo_arm64). This
just adds the register along with other required changes.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/cpu.h   | 1 +
 arch/arm64/kernel/cpufeature.c | 4 ++++
 arch/arm64/kernel/cpuinfo.c    | 1 +
 3 files changed, 6 insertions(+)

diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index e1f5ef437671..7faae6ff3ab4 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -45,6 +45,7 @@ struct cpuinfo_arm64 {
 	u32		reg_id_mmfr1;
 	u32		reg_id_mmfr2;
 	u32		reg_id_mmfr3;
+	u32		reg_id_mmfr4;
 	u32		reg_id_mmfr5;
 	u32		reg_id_pfr0;
 	u32		reg_id_pfr1;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 70c3b49aac11..42990188fb6c 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -785,6 +785,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
 		init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 		init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 		init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
+		init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
 		init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
 		init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 		init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
@@ -920,6 +921,8 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
 				      info->reg_id_mmfr2, boot->reg_id_mmfr2);
 	taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 				      info->reg_id_mmfr3, boot->reg_id_mmfr3);
+	taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
+				      info->reg_id_mmfr4, boot->reg_id_mmfr4);
 	taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
 				      info->reg_id_mmfr5, boot->reg_id_mmfr5);
 	taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
@@ -1062,6 +1065,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id)
 	read_sysreg_case(SYS_ID_MMFR1_EL1);
 	read_sysreg_case(SYS_ID_MMFR2_EL1);
 	read_sysreg_case(SYS_ID_MMFR3_EL1);
+	read_sysreg_case(SYS_ID_MMFR4_EL1);
 	read_sysreg_case(SYS_ID_MMFR5_EL1);
 	read_sysreg_case(SYS_ID_ISAR0_EL1);
 	read_sysreg_case(SYS_ID_ISAR1_EL1);
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 54579bf08f74..465ef72f061a 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -374,6 +374,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 		info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
 		info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
 		info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
+		info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
 		info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
 		info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
 		info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
-- 
2.20.1


WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, suzuki.poulose@arm.com,
	catalin.marinas@arm.com,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-kernel@vger.kernel.org, maz@kernel.org, will@kernel.org
Subject: [PATCH V4 17/17] arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context
Date: Tue, 19 May 2020 15:10:54 +0530	[thread overview]
Message-ID: <1589881254-10082-18-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1589881254-10082-1-git-send-email-anshuman.khandual@arm.com>

ID_MMFR4_EL1 has been missing in the CPU context (i.e cpuinfo_arm64). This
just adds the register along with other required changes.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/cpu.h   | 1 +
 arch/arm64/kernel/cpufeature.c | 4 ++++
 arch/arm64/kernel/cpuinfo.c    | 1 +
 3 files changed, 6 insertions(+)

diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index e1f5ef437671..7faae6ff3ab4 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -45,6 +45,7 @@ struct cpuinfo_arm64 {
 	u32		reg_id_mmfr1;
 	u32		reg_id_mmfr2;
 	u32		reg_id_mmfr3;
+	u32		reg_id_mmfr4;
 	u32		reg_id_mmfr5;
 	u32		reg_id_pfr0;
 	u32		reg_id_pfr1;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 70c3b49aac11..42990188fb6c 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -785,6 +785,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
 		init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 		init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 		init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
+		init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
 		init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
 		init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 		init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
@@ -920,6 +921,8 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
 				      info->reg_id_mmfr2, boot->reg_id_mmfr2);
 	taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 				      info->reg_id_mmfr3, boot->reg_id_mmfr3);
+	taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
+				      info->reg_id_mmfr4, boot->reg_id_mmfr4);
 	taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
 				      info->reg_id_mmfr5, boot->reg_id_mmfr5);
 	taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
@@ -1062,6 +1065,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id)
 	read_sysreg_case(SYS_ID_MMFR1_EL1);
 	read_sysreg_case(SYS_ID_MMFR2_EL1);
 	read_sysreg_case(SYS_ID_MMFR3_EL1);
+	read_sysreg_case(SYS_ID_MMFR4_EL1);
 	read_sysreg_case(SYS_ID_MMFR5_EL1);
 	read_sysreg_case(SYS_ID_ISAR0_EL1);
 	read_sysreg_case(SYS_ID_ISAR1_EL1);
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 54579bf08f74..465ef72f061a 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -374,6 +374,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 		info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
 		info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
 		info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
+		info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
 		info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
 		info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
 		info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
-- 
2.20.1


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  parent reply	other threads:[~2020-05-19  9:42 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-19  9:40 [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-19  9:40 ` Anshuman Khandual
2020-05-19  9:40 ` Anshuman Khandual
2020-05-19  9:40 ` [PATCH V4 01/17] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19  9:40 ` [PATCH V4 02/17] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19  9:40 ` [PATCH V4 03/17] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 10:44   ` Suzuki K Poulose
2020-05-19 10:44     ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 04/17] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19  9:40 ` [PATCH V4 05/17] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 10:46   ` Suzuki K Poulose
2020-05-19 10:46     ` Suzuki K Poulose
2020-05-19 10:46     ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 06/17] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 10:50   ` Suzuki K Poulose
2020-05-19 10:50     ` Suzuki K Poulose
2020-05-19 10:50     ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 07/17] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19  9:40 ` [PATCH V4 08/17] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 10:53   ` Suzuki K Poulose
2020-05-19 10:53     ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 09/17] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 10:56   ` Suzuki K Poulose
2020-05-19 10:56     ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 10/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 11:11   ` Suzuki K Poulose
2020-05-19 11:11     ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 11/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 11:13   ` Suzuki K Poulose
2020-05-19 11:13     ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 12/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 13:32   ` Suzuki K Poulose
2020-05-19 13:32     ` Suzuki K Poulose
2020-05-24 23:08     ` Anshuman Khandual
2020-05-24 23:08       ` Anshuman Khandual
2020-05-19  9:40 ` [PATCH V4 13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19 13:44   ` Suzuki K Poulose
2020-05-19 13:44     ` Suzuki K Poulose
2020-05-24  1:09     ` Anshuman Khandual
2020-05-24  1:09       ` Anshuman Khandual
2020-05-19  9:40 ` [PATCH V4 14/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-20 13:56   ` Suzuki K Poulose
2020-05-20 13:56     ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 15/17] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-20 13:57   ` Suzuki K Poulose
2020-05-20 13:57     ` Suzuki K Poulose
2020-05-24  1:08     ` Anshuman Khandual
2020-05-24  1:08       ` Anshuman Khandual
2020-05-25 10:46       ` Suzuki K Poulose
2020-05-25 10:46         ` Suzuki K Poulose
2020-05-19  9:40 ` [PATCH V4 16/17] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-05-19  9:40   ` Anshuman Khandual
2020-05-19  9:40 ` Anshuman Khandual [this message]
2020-05-19  9:40   ` [PATCH V4 17/17] arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context Anshuman Khandual
2020-05-20 13:58   ` Suzuki K Poulose
2020-05-20 13:58     ` Suzuki K Poulose
2020-05-21 15:19 ` [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Will Deacon
2020-05-21 15:19   ` Will Deacon
2020-05-21 15:19   ` Will Deacon
2020-05-25 12:39   ` Anshuman Khandual
2020-05-25 12:39     ` Anshuman Khandual
2020-05-25 12:39     ` Anshuman Khandual

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