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From: Mason Yang <masonccyang@mxic.com.tw>
To: broonie@kernel.org, tudor.ambarus@microchip.com,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	boris.brezillon@collabora.com, matthias.bgg@gmail.com
Cc: p.yadav@ti.com, juliensu@mxic.com.tw,
	linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
	linux-spi@vger.kernel.org
Subject: [PATCH v3 01/14] spi: spi-mem: allow specifying whether an op is DTR or not
Date: Thu, 28 May 2020 15:58:03 +0800	[thread overview]
Message-ID: <1590652696-8844-2-git-send-email-masonccyang@mxic.com.tw> (raw)
In-Reply-To: <1590652696-8844-1-git-send-email-masonccyang@mxic.com.tw>

From: Pratyush Yadav <p.yadav@ti.com>

Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/spi/spi-mem.c       | 3 +++
 include/linux/spi/spi-mem.h | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index adaa0c4..d8905e0 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -154,6 +154,9 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
 				   op->data.dir == SPI_MEM_DATA_OUT))
 		return false;
 
+	if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
+		return false;
+
 	return true;
 }
 EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index af9ff2f..e3dcb95 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -71,9 +71,11 @@ enum spi_mem_data_dir {
  * struct spi_mem_op - describes a SPI memory operation
  * @cmd.buswidth: number of IO lines used to transmit the command
  * @cmd.opcode: operation opcode
+ * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
  * @addr.nbytes: number of address bytes to send. Can be zero if the operation
  *		 does not need to send an address
  * @addr.buswidth: number of IO lines used to transmit the address cycles
+ * @addr.dtr: whether the address should be sent in DTR mode or not
  * @addr.val: address value. This value is always sent MSB first on the bus.
  *	      Note that only @addr.nbytes are taken into account in this
  *	      address value, so users should make sure the value fits in the
@@ -81,7 +83,9 @@ enum spi_mem_data_dir {
  * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
  *		  be zero if the operation does not require dummy bytes
  * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
+ * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
  * @data.buswidth: number of IO lanes used to send/receive the data
+ * @data.dtr: whether the data should be sent in DTR mode or not
  * @data.dir: direction of the transfer
  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
  *		 operation does not involve transferring data
@@ -91,22 +95,26 @@ enum spi_mem_data_dir {
 struct spi_mem_op {
 	struct {
 		u8 buswidth;
+		u8 dtr : 1;
 		u8 opcode;
 	} cmd;
 
 	struct {
 		u8 nbytes;
 		u8 buswidth;
+		u8 dtr : 1;
 		u64 val;
 	} addr;
 
 	struct {
 		u8 nbytes;
 		u8 buswidth;
+		u8 dtr : 1;
 	} dummy;
 
 	struct {
 		u8 buswidth;
+		u8 dtr : 1;
 		enum spi_mem_data_dir dir;
 		unsigned int nbytes;
 		union {
-- 
1.9.1


WARNING: multiple messages have this Message-ID (diff)
From: Mason Yang <masonccyang@mxic.com.tw>
To: broonie@kernel.org, tudor.ambarus@microchip.com,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	boris.brezillon@collabora.com, matthias.bgg@gmail.com
Cc: juliensu@mxic.com.tw, linux-spi@vger.kernel.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	linux-kernel@vger.kernel.org
Subject: [PATCH v3 01/14] spi: spi-mem: allow specifying whether an op is DTR or not
Date: Thu, 28 May 2020 15:58:03 +0800	[thread overview]
Message-ID: <1590652696-8844-2-git-send-email-masonccyang@mxic.com.tw> (raw)
In-Reply-To: <1590652696-8844-1-git-send-email-masonccyang@mxic.com.tw>

From: Pratyush Yadav <p.yadav@ti.com>

Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/spi/spi-mem.c       | 3 +++
 include/linux/spi/spi-mem.h | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index adaa0c4..d8905e0 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -154,6 +154,9 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
 				   op->data.dir == SPI_MEM_DATA_OUT))
 		return false;
 
+	if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
+		return false;
+
 	return true;
 }
 EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index af9ff2f..e3dcb95 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -71,9 +71,11 @@ enum spi_mem_data_dir {
  * struct spi_mem_op - describes a SPI memory operation
  * @cmd.buswidth: number of IO lines used to transmit the command
  * @cmd.opcode: operation opcode
+ * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
  * @addr.nbytes: number of address bytes to send. Can be zero if the operation
  *		 does not need to send an address
  * @addr.buswidth: number of IO lines used to transmit the address cycles
+ * @addr.dtr: whether the address should be sent in DTR mode or not
  * @addr.val: address value. This value is always sent MSB first on the bus.
  *	      Note that only @addr.nbytes are taken into account in this
  *	      address value, so users should make sure the value fits in the
@@ -81,7 +83,9 @@ enum spi_mem_data_dir {
  * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
  *		  be zero if the operation does not require dummy bytes
  * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
+ * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
  * @data.buswidth: number of IO lanes used to send/receive the data
+ * @data.dtr: whether the data should be sent in DTR mode or not
  * @data.dir: direction of the transfer
  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
  *		 operation does not involve transferring data
@@ -91,22 +95,26 @@ enum spi_mem_data_dir {
 struct spi_mem_op {
 	struct {
 		u8 buswidth;
+		u8 dtr : 1;
 		u8 opcode;
 	} cmd;
 
 	struct {
 		u8 nbytes;
 		u8 buswidth;
+		u8 dtr : 1;
 		u64 val;
 	} addr;
 
 	struct {
 		u8 nbytes;
 		u8 buswidth;
+		u8 dtr : 1;
 	} dummy;
 
 	struct {
 		u8 buswidth;
+		u8 dtr : 1;
 		enum spi_mem_data_dir dir;
 		unsigned int nbytes;
 		union {
-- 
1.9.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  reply	other threads:[~2020-05-28  7:58 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-28  7:58 [PATCH v3 00/14] mtd: spi-nor: add xSPI Octal DTR support Mason Yang
2020-05-28  7:58 ` Mason Yang
2020-05-28  7:58 ` Mason Yang [this message]
2020-05-28  7:58   ` [PATCH v3 01/14] spi: spi-mem: allow specifying whether an op is DTR or not Mason Yang
2020-05-28  7:58 ` [PATCH v3 02/14] spi: spi-mem: allow specifying a command's extension Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 03/14] mtd: spi-nor: add support for DTR protocol Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 04/14] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 05/14] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 06/14] mtd: spi-nor: sfdp: get octal mode maximum speed " Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 07/14] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 08/14] mtd: spi-nor: sfdp: parse command sequences to change octal DTR mode Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 09/14] mtd: spi-nor: core: add configuration register 2 read & write support Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 10/14] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 11/14] mtd: spi-nor: core: enable octal DTR mode when possible Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 12/14] spi: mxic: patch for octal DTR mode support Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28 21:44   ` kbuild test robot
2020-05-28 21:44     ` kbuild test robot
2020-05-28 21:44     ` kbuild test robot
2020-05-28  7:58 ` [PATCH v3 13/14] mtd: spi-nor: core: execute command sequences to change octal DTR mode Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 14/14] mtd: spi-nor: macronix: Add Octal 8D-8D-8D supports for Macronix mx25uw51245g Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  8:26 ` [PATCH v3 00/14] mtd: spi-nor: add xSPI Octal DTR support Boris Brezillon
2020-05-28  8:26   ` Boris Brezillon
2020-05-29  5:27   ` masonccyang
2020-05-29  5:27     ` masonccyang

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