From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
CK Hu <ck.hu@mediatek.com>
Cc: Jassi Brar <jassisinghbrar@gmail.com>,
Bibby Hsieh <bibby.hsieh@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v1, 2/5] arm64: dts: mt8192: add gce node
Date: Sat, 5 Dec 2020 12:15:25 +0800 [thread overview]
Message-ID: <1607141728-17307-3-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1607141728-17307-1-git-send-email-yongqiang.niu@mediatek.com>
add gce node
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 69d45c7..7c0c233 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -272,6 +273,16 @@
clock-names = "clk13m";
};
+ gce: mailbox@10228000 {
+ compatible = "mediatek,mt8192-gce";
+ reg = <0 0x10228000 0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg CLK_INFRA_GCE>,
+ <&infracfg CLK_INFRA_GCE_26M>;
+ clock-names = "gce", "gce-timer";
+ };
+
scp_adsp: syscon@10720000 {
compatible = "mediatek,mt8192-scp_adsp", "syscon";
reg = <0 0x10720000 0 0x1000>;
--
1.8.1.1.dirty
WARNING: multiple messages have this Message-ID (diff)
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
CK Hu <ck.hu@mediatek.com>
Cc: Bibby Hsieh <bibby.hsieh@mediatek.com>,
Jassi Brar <jassisinghbrar@gmail.com>,
linux-kernel@vger.kernel.org,
Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>,
linux-mediatek@lists.infradead.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1, 2/5] arm64: dts: mt8192: add gce node
Date: Sat, 5 Dec 2020 12:15:25 +0800 [thread overview]
Message-ID: <1607141728-17307-3-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1607141728-17307-1-git-send-email-yongqiang.niu@mediatek.com>
add gce node
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 69d45c7..7c0c233 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -272,6 +273,16 @@
clock-names = "clk13m";
};
+ gce: mailbox@10228000 {
+ compatible = "mediatek,mt8192-gce";
+ reg = <0 0x10228000 0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg CLK_INFRA_GCE>,
+ <&infracfg CLK_INFRA_GCE_26M>;
+ clock-names = "gce", "gce-timer";
+ };
+
scp_adsp: syscon@10720000 {
compatible = "mediatek,mt8192-scp_adsp", "syscon";
reg = <0 0x10720000 0 0x1000>;
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
CK Hu <ck.hu@mediatek.com>
Cc: Bibby Hsieh <bibby.hsieh@mediatek.com>,
Jassi Brar <jassisinghbrar@gmail.com>,
linux-kernel@vger.kernel.org,
Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>,
linux-mediatek@lists.infradead.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1, 2/5] arm64: dts: mt8192: add gce node
Date: Sat, 5 Dec 2020 12:15:25 +0800 [thread overview]
Message-ID: <1607141728-17307-3-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1607141728-17307-1-git-send-email-yongqiang.niu@mediatek.com>
add gce node
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 69d45c7..7c0c233 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -272,6 +273,16 @@
clock-names = "clk13m";
};
+ gce: mailbox@10228000 {
+ compatible = "mediatek,mt8192-gce";
+ reg = <0 0x10228000 0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg CLK_INFRA_GCE>,
+ <&infracfg CLK_INFRA_GCE_26M>;
+ clock-names = "gce", "gce-timer";
+ };
+
scp_adsp: syscon@10720000 {
compatible = "mediatek,mt8192-scp_adsp", "syscon";
reg = <0 0x10720000 0 0x1000>;
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-12-05 4:17 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-05 4:15 [PATCH v1, 0/5] support gce on mt8192 platform Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 4:15 ` [PATCH v1, 1/5] dt-binding: gce: add gce header file for mt8192 Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu [this message]
2020-12-05 4:15 ` [PATCH v1, 2/5] arm64: dts: mt8192: add gce node Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 4:15 ` [PATCH v1, 3/5] mailbox: mediatek: add control_by_sw private data Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 7:35 ` Nicolas Boichat
2020-12-05 7:35 ` Nicolas Boichat
2020-12-05 7:35 ` Nicolas Boichat
2020-12-23 0:33 ` Yongqiang Niu
2020-12-23 0:33 ` Yongqiang Niu
2020-12-23 0:33 ` Yongqiang Niu
2020-12-05 4:15 ` [PATCH v1, 4/5] soc: mediatek: cmdq: add address shift in jump Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 7:30 ` Nicolas Boichat
2020-12-05 7:30 ` Nicolas Boichat
2020-12-05 7:30 ` Nicolas Boichat
2020-12-09 15:16 ` Chun-Kuang Hu
2020-12-09 15:16 ` Chun-Kuang Hu
2020-12-09 15:16 ` Chun-Kuang Hu
2020-12-23 0:36 ` Yongqiang Niu
2020-12-23 0:36 ` Yongqiang Niu
2020-12-23 0:36 ` Yongqiang Niu
2020-12-05 4:15 ` [PATCH v1, 5/5] mailbox: cmdq: add mt8192 support Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
2020-12-05 4:15 ` Yongqiang Niu
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