All of lore.kernel.org
 help / color / mirror / Atom feed
From: dillon.minfei@gmail.com
To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com,
	alexandre.torgue@st.com, devicetree@vger.kernel.org,
	linux-stm32@st-md-mailman.stormreply.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux@armlinux.org.uk,
	vladimir.murzin@arm.com, afzal.mohd.ma@gmail.com
Cc: dillon min <dillon.minfei@gmail.com>
Subject: [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call
Date: Wed,  3 Mar 2021 16:05:10 +0800	[thread overview]
Message-ID: <1614758717-18223-2-git-send-email-dillon.minfei@gmail.com> (raw)
In-Reply-To: <1614758717-18223-1-git-send-email-dillon.minfei@gmail.com>

From: dillon min <dillon.minfei@gmail.com>

For some case, kernel not boot by u-boot(single thread),
but by rtos , as most rtos use pendsv to do context switch.

So, we need add an lr check after svc call, to find out should
use psp or msp. else register restore after svc call might be
corrupted.

Fixes: b70cd406d7fe ("ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode")
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/mm/proc-v7m.S | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 84459c1d31b8..c93d2757312d 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -137,7 +137,10 @@ __v7m_setup_cont:
 1:	cpsid	i
 	/* Calculate exc_ret */
 	orr	r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
-	ldmia	sp, {r0-r3, r12}
+	tst	lr, #EXC_RET_STACK_MASK
+	mrsne	r4, psp
+	moveq	r4, sp
+	ldmia	r4!, {r0-r3, r12}
 	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
 	mov	lr, r6			@ restore LR
 
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: dillon.minfei@gmail.com
To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com,
	alexandre.torgue@st.com, devicetree@vger.kernel.org,
	linux-stm32@st-md-mailman.stormreply.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux@armlinux.org.uk,
	vladimir.murzin@arm.com, afzal.mohd.ma@gmail.com
Cc: dillon min <dillon.minfei@gmail.com>
Subject: [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call
Date: Wed,  3 Mar 2021 16:05:10 +0800	[thread overview]
Message-ID: <1614758717-18223-2-git-send-email-dillon.minfei@gmail.com> (raw)
In-Reply-To: <1614758717-18223-1-git-send-email-dillon.minfei@gmail.com>

From: dillon min <dillon.minfei@gmail.com>

For some case, kernel not boot by u-boot(single thread),
but by rtos , as most rtos use pendsv to do context switch.

So, we need add an lr check after svc call, to find out should
use psp or msp. else register restore after svc call might be
corrupted.

Fixes: b70cd406d7fe ("ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode")
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/mm/proc-v7m.S | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 84459c1d31b8..c93d2757312d 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -137,7 +137,10 @@ __v7m_setup_cont:
 1:	cpsid	i
 	/* Calculate exc_ret */
 	orr	r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
-	ldmia	sp, {r0-r3, r12}
+	tst	lr, #EXC_RET_STACK_MASK
+	mrsne	r4, psp
+	moveq	r4, sp
+	ldmia	r4!, {r0-r3, r12}
 	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
 	mov	lr, r6			@ restore LR
 
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-03-03 13:06 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-03  8:05 [PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board support dillon.minfei
2021-03-03  8:05 ` dillon.minfei
2021-03-03  8:05 ` dillon.minfei [this message]
2021-03-03  8:05   ` [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call dillon.minfei
2021-03-03  9:52   ` Vladimir Murzin
2021-03-03  9:52     ` Vladimir Murzin
2021-03-03 13:35     ` dillon min
2021-03-03 13:35       ` dillon min
2021-03-03 14:19       ` Vladimir Murzin
2021-03-03 14:19         ` Vladimir Murzin
2021-03-04  5:42         ` dillon min
2021-03-04  5:42           ` dillon min
2021-03-04  9:02           ` Vladimir Murzin
2021-03-04  9:02             ` Vladimir Murzin
2021-03-03  8:05 ` [PATCH 2/8] Documentation: arm: stm32: Add stm32h750 value line dillon.minfei
2021-03-03  8:05   ` dillon.minfei
2021-03-03  8:05 ` [PATCH 3/8] dt-bindings: arm: stm32: Add compatible strings for ART-PI board dillon.minfei
2021-03-03  8:05   ` dillon.minfei
2021-03-08 19:50   ` Rob Herring
2021-03-08 19:50     ` Rob Herring
2021-03-03  8:05 ` [PATCH 4/8] dt-bindings: pinctrl: stm32: Add stm32h750 pinctrl dillon.minfei
2021-03-03  8:05   ` dillon.minfei
2021-03-08 19:50   ` Rob Herring
2021-03-08 19:50     ` Rob Herring
2021-03-03  8:05 ` [PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x dillon.minfei
2021-03-03  8:05   ` dillon.minfei
2021-03-11 10:40   ` Alexandre TORGUE
2021-03-11 10:40     ` Alexandre TORGUE
2021-03-11 12:23     ` dillon min
2021-03-11 12:23       ` dillon min
2021-03-11 12:54       ` [Linux-stm32] " Ahmad Fatoum
2021-03-11 12:54         ` Ahmad Fatoum
2021-03-11 13:03         ` dillon min
2021-03-11 13:03           ` dillon min
2021-03-11 13:30       ` Alexandre TORGUE
2021-03-11 13:30         ` Alexandre TORGUE
2021-03-11 14:32         ` dillon min
2021-03-11 14:32           ` dillon min
2021-03-11 14:50           ` Alexandre TORGUE
2021-03-11 14:50             ` Alexandre TORGUE
2021-03-03  8:05 ` [PATCH 6/8] ARM: dts: stm32: add stm32h750-pinctrl.dtsi dillon.minfei
2021-03-03  8:05   ` dillon.minfei
2021-03-03  8:05 ` [PATCH 7/8] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6 dillon.minfei
2021-03-03  8:05   ` dillon.minfei
2021-03-11 10:42   ` Alexandre TORGUE
2021-03-11 10:42     ` Alexandre TORGUE
2021-03-11 12:32     ` dillon min
2021-03-11 12:32       ` dillon min
2021-03-11 13:31       ` Alexandre TORGUE
2021-03-11 13:31         ` Alexandre TORGUE
2021-03-03  8:05 ` [PATCH 8/8] ARM: stm32: add initial support for stm32h750 dillon.minfei
2021-03-03  8:05   ` dillon.minfei
2021-03-11 10:43   ` Alexandre TORGUE
2021-03-11 10:43     ` Alexandre TORGUE
2021-03-11 12:34     ` dillon min
2021-03-11 12:34       ` dillon min
2021-03-10 11:47 ` [PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board support dillon min
2021-03-10 11:47   ` dillon min
2021-03-11 10:26   ` Alexandre TORGUE
2021-03-11 10:26     ` Alexandre TORGUE
2021-03-11 11:30     ` dillon min
2021-03-11 11:30       ` dillon min

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1614758717-18223-2-git-send-email-dillon.minfei@gmail.com \
    --to=dillon.minfei@gmail.com \
    --cc=afzal.mohd.ma@gmail.com \
    --cc=alexandre.torgue@st.com \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-stm32@st-md-mailman.stormreply.com \
    --cc=linux@armlinux.org.uk \
    --cc=mcoquelin.stm32@gmail.com \
    --cc=robh+dt@kernel.org \
    --cc=vladimir.murzin@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.