From: Paul Cercueil <paul@crapouillou.net>
To: Ralf Baechle <ralf@linux-mips.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>
Cc: Paul Burton <paul.burton@imgtec.com>,
Maarten ter Huurne <maarten@treewalker.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mips@linux-mips.org, linux-clk@vger.kernel.org,
Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH 04/15] clk: Add Ingenic jz4770 CGU driver
Date: Wed, 7 Jun 2017 22:04:28 +0200 [thread overview]
Message-ID: <20170607200439.24450-5-paul@crapouillou.net> (raw)
In-Reply-To: <20170607200439.24450-1-paul@crapouillou.net>
Add support for the clocks provided by the CGU in the Ingenic JZ4770
SoC.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
---
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/jz4770-cgu.c | 485 +++++++++++++++++++++++++++++++++
include/dt-bindings/clock/jz4770-cgu.h | 57 ++++
3 files changed, 543 insertions(+)
create mode 100644 drivers/clk/ingenic/jz4770-cgu.c
create mode 100644 include/dt-bindings/clock/jz4770-cgu.h
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index cd47b0664c2b..1456e4cdb562 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -1,3 +1,4 @@
obj-y += cgu.o
obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o
+obj-$(CONFIG_MACH_JZ4770) += jz4770-cgu.o
obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
new file mode 100644
index 000000000000..993db42df5fc
--- /dev/null
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -0,0 +1,485 @@
+/*
+ * JZ4770 SoC CGU driver
+ *
+ * Copyright 2017, Paul Cercueil <paul@crapouillou.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/jz4770-cgu.h>
+#include "cgu.h"
+
+/*
+ * CPM registers offset address definition
+ */
+#define CGU_REG_CPCCR 0x00
+#define CGU_REG_LCR 0x04
+#define CGU_REG_CPPCR0 0x10
+#define CGU_REG_CLKGR0 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_CLKGR1 0x28
+#define CGU_REG_CPPCR1 0x30
+#define CGU_REG_USBPCR1 0x48
+#define CGU_REG_USBCDR 0x50
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LPCDR 0x64
+#define CGU_REG_MSC0CDR 0x68
+#define CGU_REG_UHCCDR 0x6c
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7c
+#define CGU_REG_GPSCDR 0x80
+#define CGU_REG_PCMCDR 0x84
+#define CGU_REG_GPUCDR 0x88
+#define CGU_REG_MSC1CDR 0xA4
+#define CGU_REG_MSC2CDR 0xA8
+#define CGU_REG_BCHCDR 0xAC
+
+/* bits within the LCR register */
+#define LCR_LPM BIT(0) /* Low Power Mode */
+
+/* bits within the OPCR register */
+#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */
+#define OPCR_SPENDN BIT(7) /* OTG PHY suspend */
+
+/* bits within the USBPCR1 register */
+#define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
+
+static struct ingenic_cgu *cgu;
+
+static int jz4770_uhc_phy_enable(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
+
+ writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr);
+ writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1);
+ return 0;
+}
+
+static void jz4770_uhc_phy_disable(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
+
+ writel(readl(reg_usbpcr1) & ~USBPCR1_UHC_POWER, reg_usbpcr1);
+ writel(readl(reg_opcr) | OPCR_SPENDH, reg_opcr);
+}
+
+static int jz4770_uhc_phy_is_enabled(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
+
+ return !(readl(reg_opcr) & OPCR_SPENDH) &&
+ (readl(reg_usbpcr1) & USBPCR1_UHC_POWER);
+}
+
+struct clk_ops jz4770_uhc_phy_ops = {
+ .enable = jz4770_uhc_phy_enable,
+ .disable = jz4770_uhc_phy_disable,
+ .is_enabled = jz4770_uhc_phy_is_enabled,
+};
+
+static int jz4770_otg_phy_enable(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+
+ writel(readl(reg_opcr) | OPCR_SPENDN, reg_opcr);
+
+ /* Wait for the clock to be stable */
+ udelay(50);
+ return 0;
+}
+
+static void jz4770_otg_phy_disable(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+
+ writel(readl(reg_opcr) & ~OPCR_SPENDN, reg_opcr);
+}
+
+static int jz4770_otg_phy_is_enabled(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+
+ return !!(readl(reg_opcr) & OPCR_SPENDN);
+}
+
+struct clk_ops jz4770_otg_phy_ops = {
+ .enable = jz4770_otg_phy_enable,
+ .disable = jz4770_otg_phy_disable,
+ .is_enabled = jz4770_otg_phy_is_enabled,
+};
+
+static const s8 pll_od_encoding[8] = {
+ 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
+};
+
+static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
+
+ /* External clocks */
+
+ [JZ4770_CLK_EXT] = { "ext", CGU_CLK_EXT },
+ [JZ4770_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
+
+ /* PLLs */
+
+ [JZ4770_CLK_PLL0] = {
+ "pll0", CGU_CLK_PLL,
+ .parents = { JZ4770_CLK_EXT },
+ .pll = {
+ .reg = CGU_REG_CPPCR0,
+ .m_shift = 24,
+ .m_bits = 7,
+ .m_offset = 1,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 1,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_bit = 9,
+ .enable_bit = 8,
+ .stable_bit = 10,
+ },
+ },
+
+ [JZ4770_CLK_PLL1] = {
+ /* TODO: PLL1 can depend on PLL0 */
+ "pll1", CGU_CLK_PLL,
+ .parents = { JZ4770_CLK_EXT },
+ .pll = {
+ .reg = CGU_REG_CPPCR1,
+ .m_shift = 24,
+ .m_bits = 7,
+ .m_offset = 1,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 1,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .enable_bit = 7,
+ .stable_bit = 6,
+ .no_bypass_bit = true,
+ },
+ },
+
+ /* Main clocks */
+
+ [JZ4770_CLK_CCLK] = {
+ "cclk", CGU_CLK_DIV,
+ .parents = { JZ4770_CLK_PLL0, },
+ .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
+ },
+ [JZ4770_CLK_H0CLK] = {
+ "h0clk", CGU_CLK_DIV,
+ .parents = { JZ4770_CLK_PLL0, },
+ .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
+ },
+ [JZ4770_CLK_H1CLK] = {
+ "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_PLL0, },
+ .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 },
+ .gate = { CGU_REG_LCR, 30 },
+ },
+ [JZ4770_CLK_H2CLK] = {
+ "h2clk", CGU_CLK_DIV,
+ .parents = { JZ4770_CLK_PLL0, },
+ .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
+ },
+ [JZ4770_CLK_C1CLK] = {
+ "c1clk", CGU_CLK_DIV,
+ .parents = { JZ4770_CLK_PLL0, },
+ .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
+ },
+ [JZ4770_CLK_PCLK] = {
+ "pclk", CGU_CLK_DIV,
+ .parents = { JZ4770_CLK_PLL0, },
+ .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
+ },
+
+ /* Those divided clocks can connect to PLL0 or PLL1 */
+
+ [JZ4770_CLK_MMC0_MUX] = {
+ "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
+ .mux = { CGU_REG_MSC0CDR, 30, 1 },
+ .div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 },
+ .gate = { CGU_REG_MSC0CDR, 31 },
+ },
+ [JZ4770_CLK_MMC1_MUX] = {
+ "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
+ .mux = { CGU_REG_MSC1CDR, 30, 1 },
+ .div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 },
+ .gate = { CGU_REG_MSC1CDR, 31 },
+ },
+ [JZ4770_CLK_MMC2_MUX] = {
+ "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
+ .mux = { CGU_REG_MSC2CDR, 30, 1 },
+ .div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 },
+ .gate = { CGU_REG_MSC2CDR, 31 },
+ },
+ [JZ4770_CLK_CIM] = {
+ "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
+ .mux = { CGU_REG_CIMCDR, 31, 1 },
+ .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 26 },
+ },
+ [JZ4770_CLK_UHC] = {
+ "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
+ .mux = { CGU_REG_UHCCDR, 29, 1 },
+ .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 24 },
+ },
+ [JZ4770_CLK_GPU] = {
+ "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 },
+ .mux = { CGU_REG_GPUCDR, 31, 1 },
+ .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR1, 9 },
+ },
+ [JZ4770_CLK_BCH] = {
+ "bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
+ .mux = { CGU_REG_BCHCDR, 31, 1 },
+ .div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 1 },
+ },
+ [JZ4770_CLK_LPCLK_MUX] = {
+ "lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
+ .mux = { CGU_REG_LPCDR, 29, 1 },
+ .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 28 },
+ },
+ [JZ4770_CLK_GPS] = {
+ "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
+ .mux = { CGU_REG_GPSCDR, 31, 1 },
+ .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 22 },
+ },
+
+ /* Those divided clocks can connect to EXT, PLL0 or PLL1 */
+
+ [JZ4770_CLK_SSI_MUX] = {
+ "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_EXT, -1,
+ JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
+ .mux = { CGU_REG_SSICDR, 30, 2 },
+ .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 },
+ },
+ [JZ4770_CLK_PCM_MUX] = {
+ "pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_EXT, -1,
+ JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
+ .mux = { CGU_REG_PCMCDR, 30, 2 },
+ .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 },
+ },
+ [JZ4770_CLK_I2S] = {
+ "i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_EXT, -1,
+ JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
+ .mux = { CGU_REG_I2SCDR, 30, 2 },
+ .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR1, 13 },
+ },
+ [JZ4770_CLK_OTG] = {
+ "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_EXT, -1,
+ JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
+ .mux = { CGU_REG_USBCDR, 30, 2 },
+ .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 2 },
+ },
+
+ /* Gate-only clocks */
+
+ [JZ4770_CLK_SSI0] = {
+ "ssi0", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_SSI_MUX, },
+ .gate = { CGU_REG_CLKGR0, 4 },
+ },
+ [JZ4770_CLK_SSI1] = {
+ "ssi1", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_SSI_MUX, },
+ .gate = { CGU_REG_CLKGR0, 19 },
+ },
+ [JZ4770_CLK_SSI2] = {
+ "ssi2", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_SSI_MUX, },
+ .gate = { CGU_REG_CLKGR0, 20 },
+ },
+ [JZ4770_CLK_PCM0] = {
+ "pcm0", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_PCM_MUX, },
+ .gate = { CGU_REG_CLKGR1, 8 },
+ },
+ [JZ4770_CLK_PCM1] = {
+ "pcm1", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_PCM_MUX, },
+ .gate = { CGU_REG_CLKGR1, 10 },
+ },
+ [JZ4770_CLK_DMA] = {
+ "dma", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_H2CLK, },
+ .gate = { CGU_REG_CLKGR0, 21 },
+ },
+ [JZ4770_CLK_I2C0] = {
+ "i2c0", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 5 },
+ },
+ [JZ4770_CLK_I2C1] = {
+ "i2c1", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 6 },
+ },
+ [JZ4770_CLK_I2C2] = {
+ "i2c2", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR1, 15 },
+ },
+ [JZ4770_CLK_UART0] = {
+ "uart0", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 15 },
+ },
+ [JZ4770_CLK_UART1] = {
+ "uart1", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 16 },
+ },
+ [JZ4770_CLK_UART2] = {
+ "uart2", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 17 },
+ },
+ [JZ4770_CLK_UART3] = {
+ "uart3", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 18 },
+ },
+ [JZ4770_CLK_IPU] = {
+ "ipu", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_H0CLK, },
+ .gate = { CGU_REG_CLKGR0, 29 },
+ },
+ [JZ4770_CLK_ADC] = {
+ "adc", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 14 },
+ },
+ [JZ4770_CLK_AIC] = {
+ "aic", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 8 },
+ },
+ [JZ4770_CLK_AUX] = {
+ "aux", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_C1CLK, },
+ .gate = { CGU_REG_CLKGR1, 14 },
+ },
+ [JZ4770_CLK_VPU] = {
+ "vpu", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_H1CLK, },
+ .gate = { CGU_REG_CLKGR1, 7 },
+ },
+ [JZ4770_CLK_MMC0] = {
+ "mmc0", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_MMC0_MUX, },
+ .gate = { CGU_REG_CLKGR0, 3 },
+ },
+ [JZ4770_CLK_MMC1] = {
+ "mmc1", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_MMC1_MUX, },
+ .gate = { CGU_REG_CLKGR0, 11 },
+ },
+ [JZ4770_CLK_MMC2] = {
+ "mmc2", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_MMC2_MUX, },
+ .gate = { CGU_REG_CLKGR0, 12 },
+ },
+
+ /* Custom clocks */
+
+ [JZ4770_CLK_UHC_PHY] = {
+ "uhc_phy", CGU_CLK_CUSTOM,
+ .parents = { JZ4770_CLK_UHC, -1, -1, -1 },
+ .custom = { &jz4770_uhc_phy_ops },
+ },
+ [JZ4770_CLK_OTG_PHY] = {
+ "usb_phy", CGU_CLK_CUSTOM,
+ .parents = { JZ4770_CLK_OTG, -1, -1, -1 },
+ .custom = { &jz4770_otg_phy_ops },
+ },
+
+ [JZ4770_CLK_EXT512] = {
+ "ext/512", CGU_CLK_FIXDIV,
+ .parents = { JZ4770_CLK_EXT },
+ .fixdiv = { 512 },
+ },
+
+ [JZ4770_CLK_RTC] = {
+ "rtc", CGU_CLK_MUX,
+ .parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, },
+ .mux = { CGU_REG_OPCR, 2, 1},
+ },
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int jz4770_cgu_pm_suspend(void)
+{
+ u32 val;
+
+ val = readl(cgu->base + CGU_REG_LCR);
+ writel(val | LCR_LPM, cgu->base + CGU_REG_LCR);
+ return 0;
+}
+
+static void jz4770_cgu_pm_resume(void)
+{
+ u32 val;
+
+ val = readl(cgu->base + CGU_REG_LCR);
+ writel(val & ~LCR_LPM, cgu->base + CGU_REG_LCR);
+}
+
+static struct syscore_ops jz4770_cgu_pm_ops = {
+ .suspend = jz4770_cgu_pm_suspend,
+ .resume = jz4770_cgu_pm_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+static void __init jz4770_cgu_init(struct device_node *np)
+{
+ int retval;
+
+ cgu = ingenic_cgu_new(jz4770_cgu_clocks,
+ ARRAY_SIZE(jz4770_cgu_clocks), np);
+ if (!cgu)
+ pr_err("%s: failed to initialise CGU\n", __func__);
+
+ retval = ingenic_cgu_register_clocks(cgu);
+ if (retval)
+ pr_err("%s: failed to register CGU Clocks\n", __func__);
+
+#ifdef CONFIG_PM_SLEEP
+ register_syscore_ops(&jz4770_cgu_pm_ops);
+#endif
+}
+CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
diff --git a/include/dt-bindings/clock/jz4770-cgu.h b/include/dt-bindings/clock/jz4770-cgu.h
new file mode 100644
index 000000000000..54b8b2ae4a73
--- /dev/null
+++ b/include/dt-bindings/clock/jz4770-cgu.h
@@ -0,0 +1,57 @@
+/*
+ * This header provides clock numbers for the ingenic,jz4770-cgu DT binding.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
+
+#define JZ4770_CLK_EXT 0
+#define JZ4770_CLK_OSC32K 1
+#define JZ4770_CLK_PLL0 2
+#define JZ4770_CLK_PLL1 3
+#define JZ4770_CLK_CCLK 4
+#define JZ4770_CLK_H0CLK 5
+#define JZ4770_CLK_H1CLK 6
+#define JZ4770_CLK_H2CLK 7
+#define JZ4770_CLK_C1CLK 8
+#define JZ4770_CLK_PCLK 9
+#define JZ4770_CLK_MMC0_MUX 10
+#define JZ4770_CLK_MMC0 11
+#define JZ4770_CLK_MMC1_MUX 12
+#define JZ4770_CLK_MMC1 13
+#define JZ4770_CLK_MMC2_MUX 14
+#define JZ4770_CLK_MMC2 15
+#define JZ4770_CLK_CIM 16
+#define JZ4770_CLK_UHC 17
+#define JZ4770_CLK_GPU 18
+#define JZ4770_CLK_BCH 19
+#define JZ4770_CLK_LPCLK_MUX 20
+#define JZ4770_CLK_GPS 21
+#define JZ4770_CLK_SSI_MUX 22
+#define JZ4770_CLK_PCM_MUX 23
+#define JZ4770_CLK_I2S 24
+#define JZ4770_CLK_OTG 25
+#define JZ4770_CLK_SSI0 26
+#define JZ4770_CLK_SSI1 27
+#define JZ4770_CLK_SSI2 28
+#define JZ4770_CLK_PCM0 29
+#define JZ4770_CLK_PCM1 30
+#define JZ4770_CLK_DMA 31
+#define JZ4770_CLK_I2C0 32
+#define JZ4770_CLK_I2C1 33
+#define JZ4770_CLK_I2C2 34
+#define JZ4770_CLK_UART0 35
+#define JZ4770_CLK_UART1 36
+#define JZ4770_CLK_UART2 37
+#define JZ4770_CLK_UART3 38
+#define JZ4770_CLK_IPU 39
+#define JZ4770_CLK_ADC 40
+#define JZ4770_CLK_AIC 41
+#define JZ4770_CLK_AUX 42
+#define JZ4770_CLK_VPU 43
+#define JZ4770_CLK_UHC_PHY 44
+#define JZ4770_CLK_OTG_PHY 45
+#define JZ4770_CLK_EXT512 46
+#define JZ4770_CLK_RTC 47
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */
--
2.11.0
next prev parent reply other threads:[~2017-06-07 20:08 UTC|newest]
Thread overview: 109+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-07 20:04 [PATCH 00/15] Ingenic JZ4770 and GCW Zero patchset Paul Cercueil
2017-06-07 20:04 ` Paul Cercueil
2017-06-07 20:04 ` [PATCH 01/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 01/17] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 02/17] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 03/17] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 04/17] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 05/17] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 06/17] serial: core: Make uart_parse_options take const char* argument Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 07/17] serial: 8250_ingenic: Add support for the JZ4770 SoC Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 08/17] serial: 8250_ingenic: Parse earlycon options Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 09/17] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 10/17] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2017-06-20 15:18 ` Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 11/17] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 12/17] MIPS: ingenic: Add machine info for supported boards Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 13/17] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 14/17] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 15/17] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil
2017-06-22 7:21 ` Marcin Nowakowski
2017-06-22 7:21 ` Marcin Nowakowski
2017-06-22 7:21 ` Marcin Nowakowski
2017-06-26 13:32 ` Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 16/17] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2017-06-20 15:18 ` [PATCH v2 17/17] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2017-06-21 21:50 ` [PATCH v2 01/17] clk: ingenic: Use const pointer to clk_ops in struct Stephen Boyd
2017-06-26 13:34 ` Paul Cercueil
2017-07-02 16:29 ` [PATCH v3 00/18] JZ4770 support Paul Cercueil
2017-07-02 16:29 ` [PATCH v3 01/18] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2017-07-12 23:20 ` Stephen Boyd
2017-07-13 10:07 ` [PATCH v3 01/18] clk: ingenic: Use const pointer to clk_ops in struct, Paul Cercueil
2017-07-13 10:07 ` Paul Cercueil
2017-07-13 11:49 ` [PATCH v3 01/18] clk: ingenic: Use const pointer to clk_ops in struct Ralf Baechle
2017-07-13 11:49 ` Ralf Baechle
2017-07-13 17:50 ` Stephen Boyd
2017-07-13 17:50 ` Stephen Boyd
2017-12-28 13:56 ` [PATCH v4 00/15] Ingenic JZ4770 and GCW Zero support Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 01/15] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2017-12-28 13:56 ` Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 02/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2017-12-28 18:36 ` Stephen Boyd
2017-12-28 13:56 ` [PATCH v4 03/15] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2017-12-28 18:36 ` Stephen Boyd
2017-12-28 13:56 ` [PATCH v4 04/15] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2017-12-28 18:39 ` Stephen Boyd
2017-12-28 13:56 ` [PATCH v4 05/15] dt-bindings: clock: Add jz4770-cgu.h header Paul Cercueil
2017-12-28 18:36 ` Stephen Boyd
2017-12-28 13:56 ` [PATCH v4 06/15] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2017-12-28 18:38 ` Stephen Boyd
2017-12-29 12:55 ` Philippe Ombredanne
2017-12-29 12:55 ` Philippe Ombredanne
2017-12-29 12:55 ` Philippe Ombredanne
2017-12-29 15:02 ` Paul Cercueil
2017-12-29 15:02 ` Paul Cercueil
2017-12-29 15:02 ` Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 07/15] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 08/15] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2017-12-28 13:56 ` Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 09/15] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 10/15] MIPS: ingenic: Add machine info for supported boards Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 11/15] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 12/15] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 13/15] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 14/15] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2017-12-28 13:56 ` [PATCH v4 15/15] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2017-12-28 13:56 ` Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 02/18] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 03/18] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 04/18] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 05/18] dt-bindings: clock: Add jz4770-cgu.h header Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 06/18] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 07/18] serial: core: Make uart_parse_options take const char* argument Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 08/18] serial: 8250_ingenic: Add support for the JZ4770 SoC Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 09/18] serial: 8250_ingenic: Parse earlycon options Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 10/18] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 11/18] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 12/18] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 13/18] MIPS: ingenic: Add machine info for supported boards Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 14/18] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 15/18] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 16/18] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 17/18] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2017-07-02 16:30 ` [PATCH v3 18/18] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2017-06-07 20:04 ` [PATCH 02/15] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2017-06-07 20:04 ` [PATCH 03/15] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2017-06-07 20:04 ` Paul Cercueil [this message]
2017-06-07 20:59 ` [PATCH 04/15] clk: Add Ingenic jz4770 CGU driver Stephen Boyd
2017-06-07 20:59 ` Stephen Boyd
2017-06-08 8:40 ` Maarten ter Huurne
2017-06-08 21:10 ` Paul Cercueil
2017-06-26 13:50 ` Paul Cercueil
2017-06-26 22:49 ` Stephen Boyd
2017-06-07 20:04 ` [PATCH 05/15] serial: 8250_ingenic: Add support for the JZ4770 SoC Paul Cercueil
2017-06-09 14:22 ` Rob Herring
2017-06-09 14:22 ` Rob Herring
2017-06-07 20:04 ` [PATCH 06/15] serial: 8250_ingenic: Parse earlycon options Paul Cercueil
2017-06-08 7:31 ` Marcin Nowakowski
2017-06-08 7:31 ` Marcin Nowakowski
2017-06-08 21:12 ` Paul Cercueil
2017-06-07 20:04 ` [PATCH 07/15] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2017-06-07 20:04 ` [PATCH 08/15] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2017-06-07 20:04 ` [PATCH 09/15] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2017-06-07 20:04 ` [PATCH 10/15] MIPS: ingenic: Add machine info for supported boards Paul Cercueil
2017-06-07 20:04 ` [PATCH 11/15] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2017-06-07 20:04 ` [PATCH 12/15] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2017-06-07 20:04 ` [PATCH 13/15] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil
2017-06-07 20:04 ` [PATCH 14/15] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2017-06-09 14:24 ` Rob Herring
2017-06-07 20:04 ` [PATCH 15/15] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
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