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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, David Hildenbrand <david@redhat.com>
Subject: [Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte
Date: Fri, 23 Jun 2017 09:22:40 -0700	[thread overview]
Message-ID: <20170623162241.8964-15-rth@twiddle.net> (raw)
In-Reply-To: <20170623162241.8964-1-rth@twiddle.net>

From: David Hildenbrand <david@redhat.com>

If only the page index is set, most likely we don't have a valid
virtual address. Let's do a full tlb flush for that case.

Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20170622094151.28633-3-david@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target/s390x/mem_helper.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 182c46f..20cef9a 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1630,16 +1630,23 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
     /* XXX we exploit the fact that Linux passes the exact virtual
        address here - it's not obliged to! */
     if (m4 & 1) {
-        tlb_flush_page(cs, page);
-    } else {
-        tlb_flush_page_all_cpus_synced(cs, page);
-    }
-
-    /* XXX 31-bit hack */
-    if (m4 & 1) {
-        tlb_flush_page(cs, page ^ 0x80000000);
+        if (vaddr & ~VADDR_PX) {
+            tlb_flush_page(cs, page);
+            /* XXX 31-bit hack */
+            tlb_flush_page(cs, page ^ 0x80000000);
+        } else {
+            /* looks like we don't have a valid virtual address */
+            tlb_flush(cs);
+        }
     } else {
-        tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000);
+        if (vaddr & ~VADDR_PX) {
+            tlb_flush_page_all_cpus_synced(cs, page);
+            /* XXX 31-bit hack */
+            tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000);
+        } else {
+            /* looks like we don't have a valid virtual address */
+            tlb_flush_all_cpus_synced(cs);
+        }
     }
 }
 
-- 
2.9.4

  parent reply	other threads:[~2017-06-23 16:23 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-23 16:22 [Qemu-devel] [PULL 00/15] Queued target/s390x patches Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 01/15] target/s390x: Map existing FAC_* names to S390_FEAT_* names Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 02/15] target/s390x: change PSW_SHIFT_KEY Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 03/15] target/s390x: implement mvcos instruction Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 04/15] target/s390x: Mark FPSEH facility as available Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 05/15] target/s390x: Implement load-on-condition-2 insns Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 07/15] target/s390x: Mark STFLE_53 facility as available Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 09/15] target/s390x: Implement processor-assist insn Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 10/15] target/s390x: Mark STFLE_49 facility as available Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 13/15] target/s390x: Indicate and check for local tlb clearing Richard Henderson
2017-06-23 16:22 ` Richard Henderson [this message]
2017-06-23 16:22 ` [Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction Richard Henderson
2017-06-26  9:17 ` [Qemu-devel] [PULL 00/15] Queued target/s390x patches Peter Maydell

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