From: codekipper@gmail.com
To: maxime.ripard@free-electrons.com
Cc: linux-arm-kernel@lists.infradead.org,
linux-sunxi@googlegroups.com, lgirdwood@gmail.com,
broonie@kernel.org, linux-kernel@vger.kernel.org,
alsa-devel@alsa-project.org, be17068@iperbole.bo.it,
Marcus Cooper <codekipper@gmail.com>
Subject: [PATCH v3 07/12] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup
Date: Sat, 29 Jul 2017 16:17:48 +0200 [thread overview]
Message-ID: <20170729141753.20174-8-codekipper@gmail.com> (raw)
In-Reply-To: <20170729141753.20174-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
On newer SoCs the bit fields for the blck and lrclk polarity are in
a different locations. Use regmap fields to set the polarity bits
as intended.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 45 ++++++++++++++++++++++++++++++++-------------
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 171df99a267e..90daa974bd27 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -50,6 +50,8 @@
#define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
#define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
#define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
+#define SUN4I_I2S_FMT0_POLARITY_INVERTED (1)
+#define SUN4I_I2S_FMT0_POLARITY_NORMAL (0)
#define SUN4I_I2S_FMT1_REG 0x08
#define SUN4I_I2S_FIFO_TX_REG 0x0c
@@ -101,6 +103,8 @@
* @fmt_offset: Value by which wss and sr needs to be adjusted.
* @field_fmt_set_wss: regmap field to set word select size.
* @field_fmt_set_sr: regmap field to set sample resolution.
+ * @field_fmt_set_bclk_polarity: regmap field to set clk polarity.
+ * @field_fmt_set_lrclk_polarity: regmap field to set frame polarity.
* @field_txchanmap: location of the tx channel mapping register.
* @field_rxchanmap: location of the rx channel mapping register.
* @field_txchansel: location of the tx channel select bit fields.
@@ -117,6 +121,8 @@ struct sun4i_i2s_quirks {
/* Register fields for i2s */
struct reg_field field_fmt_set_wss;
struct reg_field field_fmt_set_sr;
+ struct reg_field field_fmt_set_bclk_polarity;
+ struct reg_field field_fmt_set_lrclk_polarity;
struct reg_field field_txchanmap;
struct reg_field field_rxchanmap;
struct reg_field field_txchansel;
@@ -137,6 +143,8 @@ struct sun4i_i2s {
/* Register fields for i2s */
struct regmap_field *field_fmt_set_wss;
struct regmap_field *field_fmt_set_sr;
+ struct regmap_field *field_fmt_set_bclk_polarity;
+ struct regmap_field *field_fmt_set_lrclk_polarity;
struct regmap_field *field_txchanmap;
struct regmap_field *field_rxchanmap;
struct regmap_field *field_txchansel;
@@ -332,6 +340,8 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
u32 val;
+ u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
+ u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -356,32 +366,25 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
+ lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL;
+ bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
- val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL;
+ lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_NF:
- /* Nothing to do for both normal cases */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL;
break;
default:
return -EINVAL;
}
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
- SUN4I_I2S_FMT0_BCLK_POLARITY_MASK |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK,
- val);
+ regmap_field_write(i2s->field_fmt_set_bclk_polarity, bclk_polarity);
+ regmap_field_write(i2s->field_fmt_set_lrclk_polarity, lrclk_polarity);
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -709,6 +712,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
+ .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -721,6 +726,8 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
+ .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -741,6 +748,18 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2
if (IS_ERR(i2s->field_fmt_set_sr))
return PTR_ERR(i2s->field_fmt_set_sr);
+ i2s->field_fmt_set_bclk_polarity =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_fmt_set_bclk_polarity);
+ if (IS_ERR(i2s->field_fmt_set_bclk_polarity))
+ return PTR_ERR(i2s->field_fmt_set_bclk_polarity);
+
+ i2s->field_fmt_set_lrclk_polarity =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_fmt_set_lrclk_polarity);
+ if (IS_ERR(i2s->field_fmt_set_lrclk_polarity))
+ return PTR_ERR(i2s->field_fmt_set_lrclk_polarity);
+
i2s->field_txchanmap =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_txchanmap);
--
2.13.3
WARNING: multiple messages have this Message-ID (diff)
From: codekipper-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
be17068-p0aYb1w59bq9tCD/VL7h6Q@public.gmane.org,
Marcus Cooper
<codekipper-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: [PATCH v3 07/12] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup
Date: Sat, 29 Jul 2017 16:17:48 +0200 [thread overview]
Message-ID: <20170729141753.20174-8-codekipper@gmail.com> (raw)
In-Reply-To: <20170729141753.20174-1-codekipper-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Marcus Cooper <codekipper-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On newer SoCs the bit fields for the blck and lrclk polarity are in
a different locations. Use regmap fields to set the polarity bits
as intended.
Signed-off-by: Marcus Cooper <codekipper-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
sound/soc/sunxi/sun4i-i2s.c | 45 ++++++++++++++++++++++++++++++++-------------
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 171df99a267e..90daa974bd27 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -50,6 +50,8 @@
#define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
#define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
#define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
+#define SUN4I_I2S_FMT0_POLARITY_INVERTED (1)
+#define SUN4I_I2S_FMT0_POLARITY_NORMAL (0)
#define SUN4I_I2S_FMT1_REG 0x08
#define SUN4I_I2S_FIFO_TX_REG 0x0c
@@ -101,6 +103,8 @@
* @fmt_offset: Value by which wss and sr needs to be adjusted.
* @field_fmt_set_wss: regmap field to set word select size.
* @field_fmt_set_sr: regmap field to set sample resolution.
+ * @field_fmt_set_bclk_polarity: regmap field to set clk polarity.
+ * @field_fmt_set_lrclk_polarity: regmap field to set frame polarity.
* @field_txchanmap: location of the tx channel mapping register.
* @field_rxchanmap: location of the rx channel mapping register.
* @field_txchansel: location of the tx channel select bit fields.
@@ -117,6 +121,8 @@ struct sun4i_i2s_quirks {
/* Register fields for i2s */
struct reg_field field_fmt_set_wss;
struct reg_field field_fmt_set_sr;
+ struct reg_field field_fmt_set_bclk_polarity;
+ struct reg_field field_fmt_set_lrclk_polarity;
struct reg_field field_txchanmap;
struct reg_field field_rxchanmap;
struct reg_field field_txchansel;
@@ -137,6 +143,8 @@ struct sun4i_i2s {
/* Register fields for i2s */
struct regmap_field *field_fmt_set_wss;
struct regmap_field *field_fmt_set_sr;
+ struct regmap_field *field_fmt_set_bclk_polarity;
+ struct regmap_field *field_fmt_set_lrclk_polarity;
struct regmap_field *field_txchanmap;
struct regmap_field *field_rxchanmap;
struct regmap_field *field_txchansel;
@@ -332,6 +340,8 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
u32 val;
+ u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
+ u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -356,32 +366,25 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
+ lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL;
+ bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
- val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL;
+ lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_NF:
- /* Nothing to do for both normal cases */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL;
break;
default:
return -EINVAL;
}
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
- SUN4I_I2S_FMT0_BCLK_POLARITY_MASK |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK,
- val);
+ regmap_field_write(i2s->field_fmt_set_bclk_polarity, bclk_polarity);
+ regmap_field_write(i2s->field_fmt_set_lrclk_polarity, lrclk_polarity);
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -709,6 +712,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
+ .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -721,6 +726,8 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
+ .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -741,6 +748,18 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2
if (IS_ERR(i2s->field_fmt_set_sr))
return PTR_ERR(i2s->field_fmt_set_sr);
+ i2s->field_fmt_set_bclk_polarity =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_fmt_set_bclk_polarity);
+ if (IS_ERR(i2s->field_fmt_set_bclk_polarity))
+ return PTR_ERR(i2s->field_fmt_set_bclk_polarity);
+
+ i2s->field_fmt_set_lrclk_polarity =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_fmt_set_lrclk_polarity);
+ if (IS_ERR(i2s->field_fmt_set_lrclk_polarity))
+ return PTR_ERR(i2s->field_fmt_set_lrclk_polarity);
+
i2s->field_txchanmap =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_txchanmap);
--
2.13.3
WARNING: multiple messages have this Message-ID (diff)
From: codekipper@gmail.com (codekipper at gmail.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 07/12] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup
Date: Sat, 29 Jul 2017 16:17:48 +0200 [thread overview]
Message-ID: <20170729141753.20174-8-codekipper@gmail.com> (raw)
In-Reply-To: <20170729141753.20174-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
On newer SoCs the bit fields for the blck and lrclk polarity are in
a different locations. Use regmap fields to set the polarity bits
as intended.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 45 ++++++++++++++++++++++++++++++++-------------
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 171df99a267e..90daa974bd27 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -50,6 +50,8 @@
#define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
#define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
#define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
+#define SUN4I_I2S_FMT0_POLARITY_INVERTED (1)
+#define SUN4I_I2S_FMT0_POLARITY_NORMAL (0)
#define SUN4I_I2S_FMT1_REG 0x08
#define SUN4I_I2S_FIFO_TX_REG 0x0c
@@ -101,6 +103,8 @@
* @fmt_offset: Value by which wss and sr needs to be adjusted.
* @field_fmt_set_wss: regmap field to set word select size.
* @field_fmt_set_sr: regmap field to set sample resolution.
+ * @field_fmt_set_bclk_polarity: regmap field to set clk polarity.
+ * @field_fmt_set_lrclk_polarity: regmap field to set frame polarity.
* @field_txchanmap: location of the tx channel mapping register.
* @field_rxchanmap: location of the rx channel mapping register.
* @field_txchansel: location of the tx channel select bit fields.
@@ -117,6 +121,8 @@ struct sun4i_i2s_quirks {
/* Register fields for i2s */
struct reg_field field_fmt_set_wss;
struct reg_field field_fmt_set_sr;
+ struct reg_field field_fmt_set_bclk_polarity;
+ struct reg_field field_fmt_set_lrclk_polarity;
struct reg_field field_txchanmap;
struct reg_field field_rxchanmap;
struct reg_field field_txchansel;
@@ -137,6 +143,8 @@ struct sun4i_i2s {
/* Register fields for i2s */
struct regmap_field *field_fmt_set_wss;
struct regmap_field *field_fmt_set_sr;
+ struct regmap_field *field_fmt_set_bclk_polarity;
+ struct regmap_field *field_fmt_set_lrclk_polarity;
struct regmap_field *field_txchanmap;
struct regmap_field *field_rxchanmap;
struct regmap_field *field_txchansel;
@@ -332,6 +340,8 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
u32 val;
+ u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
+ u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -356,32 +366,25 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
+ lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL;
+ bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
- val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED |
- SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL;
+ lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_NF:
- /* Nothing to do for both normal cases */
- val = SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL;
break;
default:
return -EINVAL;
}
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
- SUN4I_I2S_FMT0_BCLK_POLARITY_MASK |
- SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK,
- val);
+ regmap_field_write(i2s->field_fmt_set_bclk_polarity, bclk_polarity);
+ regmap_field_write(i2s->field_fmt_set_lrclk_polarity, lrclk_polarity);
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -709,6 +712,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
+ .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -721,6 +726,8 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
+ .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -741,6 +748,18 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2
if (IS_ERR(i2s->field_fmt_set_sr))
return PTR_ERR(i2s->field_fmt_set_sr);
+ i2s->field_fmt_set_bclk_polarity =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_fmt_set_bclk_polarity);
+ if (IS_ERR(i2s->field_fmt_set_bclk_polarity))
+ return PTR_ERR(i2s->field_fmt_set_bclk_polarity);
+
+ i2s->field_fmt_set_lrclk_polarity =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_fmt_set_lrclk_polarity);
+ if (IS_ERR(i2s->field_fmt_set_lrclk_polarity))
+ return PTR_ERR(i2s->field_fmt_set_lrclk_polarity);
+
i2s->field_txchanmap =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_txchanmap);
--
2.13.3
next prev parent reply other threads:[~2017-07-29 14:18 UTC|newest]
Thread overview: 103+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-29 14:17 [PATCH v3 00/12] ASoC: Add I2S support for Allwinner H3 SoCs codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper
2017-07-29 14:17 ` [PATCH v3 01/12] ASoC: sun4i-i2s: Extend quirks scope codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-01 2:50 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-01 2:50 ` Chen-Yu Tsai
2017-08-01 2:50 ` Chen-Yu Tsai
2017-08-01 14:16 ` Applied "ASoC: sun4i-i2s: Extend quirks scope" to the asoc tree Mark Brown
2017-08-01 14:16 ` Mark Brown
2017-08-01 14:16 ` Mark Brown
2017-07-29 14:17 ` [PATCH v3 02/12] ASoC: sun4i-i2s: Add clkdiv offsets to quirks codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-01 2:55 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-01 2:55 ` Chen-Yu Tsai
2017-08-01 2:55 ` Chen-Yu Tsai
2017-08-07 6:20 ` [linux-sunxi] " Code Kipper
2017-08-07 6:20 ` Code Kipper
2017-07-29 14:17 ` [PATCH v3 03/12] ASoC: sun4i-i2s: Add regmap config " codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-01 8:10 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-01 8:10 ` Chen-Yu Tsai
2017-08-01 8:10 ` Chen-Yu Tsai
2017-08-14 16:43 ` Applied "ASoC: sun4i-i2s: Add regmap config to quirks" to the asoc tree Mark Brown
2017-08-14 16:43 ` Mark Brown
2017-08-14 16:43 ` Mark Brown
2017-07-29 14:17 ` [PATCH v3 04/12] ASoC: sun4i-i2s: Add TX FIFO offset to quirks codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-01 8:18 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-01 8:18 ` Chen-Yu Tsai
2017-08-01 8:18 ` Chen-Yu Tsai
2017-08-14 16:43 ` Applied "ASoC: sun4i-i2s: Add TX FIFO offset to quirks" to the asoc tree Mark Brown
2017-08-14 16:43 ` Mark Brown
2017-08-14 16:43 ` Mark Brown
2017-07-29 14:17 ` [PATCH v3 05/12] ASoC: sun4i-i2s: Add regmap fields for channels codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-07-30 16:43 ` [alsa-devel] " kbuild test robot
2017-07-30 16:43 ` kbuild test robot
2017-07-30 16:43 ` kbuild test robot
2017-07-30 16:43 ` [PATCH] ASoC: sun4i-i2s: fix ptr_ret.cocci warnings kbuild test robot
2017-07-30 16:43 ` kbuild test robot
2017-07-30 16:43 ` kbuild test robot
2017-08-01 8:31 ` [linux-sunxi] [PATCH v3 05/12] ASoC: sun4i-i2s: Add regmap fields for channels Chen-Yu Tsai
2017-08-01 8:31 ` Chen-Yu Tsai
2017-08-01 8:31 ` Chen-Yu Tsai
2017-08-07 7:39 ` [linux-sunxi] " Code Kipper
2017-08-07 7:39 ` Code Kipper
2017-08-07 7:39 ` Code Kipper
2017-07-29 14:17 ` [PATCH v3 06/12] ASoC: sun4i-i2s: Add changes for wss and sr codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-01 8:49 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-01 8:49 ` Chen-Yu Tsai
2017-08-01 8:49 ` Chen-Yu Tsai
2017-08-02 3:06 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-02 3:06 ` Chen-Yu Tsai
2017-08-02 3:06 ` Chen-Yu Tsai
2017-07-29 14:17 ` codekipper [this message]
2017-07-29 14:17 ` [PATCH v3 07/12] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-02 3:09 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-02 3:09 ` Chen-Yu Tsai
2017-08-02 3:09 ` Chen-Yu Tsai
2017-07-29 14:17 ` [PATCH v3 08/12] ASoC: sun4i-i2s: Add mclk enable regmap field codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-02 3:20 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-02 3:20 ` Chen-Yu Tsai
2017-08-02 3:20 ` Chen-Yu Tsai
2017-07-29 14:17 ` [PATCH v3 09/12] ASoC: sun4i-i2s: Add regmap field to set format codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-02 3:32 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-02 3:32 ` Chen-Yu Tsai
2017-08-02 3:32 ` Chen-Yu Tsai
2017-07-29 14:17 ` [PATCH v3 10/12] ASoC: sun4i-i2s: Check for slave select bit codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-02 3:50 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-02 3:50 ` Chen-Yu Tsai
2017-07-29 14:17 ` [PATCH v3 11/12] ASoC: sun4i-i2s: Update global enable with bitmask codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-02 3:55 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-02 3:55 ` Chen-Yu Tsai
2017-08-02 3:55 ` Chen-Yu Tsai
2017-07-29 14:17 ` [PATCH v3 12/12] ASoC: sun4i-i2s: Add support for H3 codekipper
2017-07-29 14:17 ` codekipper at gmail.com
2017-07-29 14:17 ` codekipper-Re5JQEeQqe8AvxtiuMwx3w
2017-08-02 4:37 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-02 4:37 ` Chen-Yu Tsai
2017-08-02 4:37 ` Chen-Yu Tsai
2017-07-31 7:05 ` [linux-sunxi] [PATCH v3 00/12] ASoC: Add I2S support for Allwinner H3 SoCs Olliver Schinagl
2017-07-31 7:05 ` Olliver Schinagl
2017-07-31 7:05 ` Olliver Schinagl
2017-07-31 14:22 ` [linux-sunxi] " Code Kipper
2017-07-31 14:22 ` Code Kipper
2017-07-31 14:22 ` Code Kipper
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