From: Jerome Brunet <jbrunet@baylibre.com> To: Neil Armstrong <narmstrong@baylibre.com>, Kevin Hilman <khilman@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, Michael Turquette <mturquette@baylibre.com>, Carlo Caione <carlo@caione.org>, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/19] clk: meson: remove obsolete comments Date: Wed, 31 Jan 2018 19:09:30 +0100 [thread overview] Message-ID: <20180131180945.18025-5-jbrunet@baylibre.com> (raw) In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> Over time things changes in CCF and issues have been fixed in meson controllers. Now, clk81 is decently modeled by read-only PLLs, a mux, a divider and a gate. We can remove the FIXME comments related to clk81. Also remove the comment about devm_clk_hw_register, as there is apparently nothing wrong with it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/clk/meson/axg.c | 5 ----- drivers/clk/meson/gxbb.c | 6 ------ drivers/clk/meson/meson8b.c | 1 - 3 files changed, 12 deletions(-) diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 81565b025b70..f84927e76f88 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -411,11 +411,6 @@ static struct meson_clk_mpll axg_mpll3 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e6adab49c0ba..6609024eee00 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -575,12 +575,6 @@ static struct meson_clk_mpll gxbb_mpll2 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ - static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index ffadad27375e..db017c29a84c 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -849,7 +849,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) if (!meson8b_hw_onecell_data.hws[i]) continue; - /* FIXME convert to devm_clk_register */ ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]); if (ret) return ret; -- 2.14.3
WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet) To: linus-amlogic@lists.infradead.org Subject: [PATCH 04/19] clk: meson: remove obsolete comments Date: Wed, 31 Jan 2018 19:09:30 +0100 [thread overview] Message-ID: <20180131180945.18025-5-jbrunet@baylibre.com> (raw) In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> Over time things changes in CCF and issues have been fixed in meson controllers. Now, clk81 is decently modeled by read-only PLLs, a mux, a divider and a gate. We can remove the FIXME comments related to clk81. Also remove the comment about devm_clk_hw_register, as there is apparently nothing wrong with it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/clk/meson/axg.c | 5 ----- drivers/clk/meson/gxbb.c | 6 ------ drivers/clk/meson/meson8b.c | 1 - 3 files changed, 12 deletions(-) diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 81565b025b70..f84927e76f88 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -411,11 +411,6 @@ static struct meson_clk_mpll axg_mpll3 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e6adab49c0ba..6609024eee00 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -575,12 +575,6 @@ static struct meson_clk_mpll gxbb_mpll2 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ - static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index ffadad27375e..db017c29a84c 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -849,7 +849,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) if (!meson8b_hw_onecell_data.hws[i]) continue; - /* FIXME convert to devm_clk_register */ ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]); if (ret) return ret; -- 2.14.3
next prev parent reply other threads:[~2018-01-31 18:14 UTC|newest] Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-01-31 18:09 [PATCH 00/19] clk: meson: use regmap in clock controllers Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 01/19] clk: meson: use dev pointer where possible Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 02/19] clk: meson: use devm_of_clk_add_hw_provider Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 03/19] clk: meson: only one loop index is necessary in probe Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet [this message] 2018-01-31 18:09 ` [PATCH 04/19] clk: meson: remove obsolete comments Jerome Brunet 2018-01-31 18:09 ` [PATCH 05/19] clk: meson: add regmap clocks Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-02-08 7:33 ` Yixun Lan 2018-02-08 7:33 ` Yixun Lan 2018-02-08 8:07 ` Jerome Brunet 2018-02-08 8:07 ` Jerome Brunet 2018-02-08 8:07 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 06/19] clk: meson: switch gxbb ao_clk to clk_regmap Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 07/19] clk: meson: remove superseded aoclk_gate_regmap Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 08/19] clk: meson: add regmap to the clock controllers Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-02-03 18:53 ` Martin Blumenstingl 2018-02-03 18:53 ` Martin Blumenstingl 2018-02-05 9:51 ` Jerome Brunet 2018-02-05 9:51 ` Jerome Brunet 2018-02-05 9:51 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 09/19] clk: meson: migrate gates to clk_regmap Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 10/19] clk: meson: migrate dividers " Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 11/19] clk: meson: migrate muxes " Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 12/19] clk: meson: add regmap helpers for parm Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 13/19] clk: meson: migrate mplls clocks to clk_regmap Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 14/19] clk: meson: migrate the audio divider clock " Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 15/19] clk: meson: migrate plls clocks " Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 16/19] clk: meson: split divider and gate part of mpll Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 17/19] clk: meson: rework meson8b cpu clock Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-02-03 18:46 ` Martin Blumenstingl 2018-02-03 18:46 ` Martin Blumenstingl 2018-02-05 9:49 ` Jerome Brunet 2018-02-05 9:49 ` Jerome Brunet 2018-02-05 9:49 ` Jerome Brunet 2018-01-31 18:09 ` [PATCH 18/19] clk: meson: remove obsolete cpu_clk Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet 2018-02-03 18:48 ` Martin Blumenstingl 2018-02-03 18:48 ` Martin Blumenstingl 2018-01-31 18:09 ` [PATCH 19/19] clk: meson: use hhi syscon if available Jerome Brunet 2018-01-31 18:09 ` Jerome Brunet
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