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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
	marc.zyngier@arm.com, cdall@kernel.org, eric.auger@redhat.com,
	pbonzini@redhat.com, rkrcmar@redhat.com, will.deacon@arm.com,
	catalin.marinas@arm.com, james.morse@arm.com,
	dave.martin@arm.com, julien.grall@arm.com,
	linux-kernel@vger.kernel.org, suzuki.poulose@arm.com
Subject: [PATCH v5 05/18] kvm: arm64: Clean up VTCR_EL2 initialisation
Date: Mon, 17 Sep 2018 11:41:27 +0100	[thread overview]
Message-ID: <20180917104144.19188-6-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20180917104144.19188-1-suzuki.poulose@arm.com>

Use the new helper for converting the parange to the physical shift.
Also, add the missing definitions for the VTCR_EL2 register fields
and use them instead of hard coding numbers.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changs sinec v3
 - Update comment about reserved bits
 - Added Reviewed-by from Eric
---
 arch/arm64/include/asm/kvm_arm.h |  3 +++
 arch/arm64/kvm/hyp/s2-setup.c    | 34 ++++++++------------------------
 2 files changed, 11 insertions(+), 26 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index aa45df752a16..5f807b680a5f 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -107,6 +107,7 @@
 #define VTCR_EL2_RES1		(1 << 31)
 #define VTCR_EL2_HD		(1 << 22)
 #define VTCR_EL2_HA		(1 << 21)
+#define VTCR_EL2_PS_SHIFT	TCR_EL2_PS_SHIFT
 #define VTCR_EL2_PS_MASK	TCR_EL2_PS_MASK
 #define VTCR_EL2_TG0_MASK	TCR_TG0_MASK
 #define VTCR_EL2_TG0_4K		TCR_TG0_4K
@@ -127,6 +128,8 @@
 #define VTCR_EL2_VS_8BIT	(0 << VTCR_EL2_VS_SHIFT)
 #define VTCR_EL2_VS_16BIT	(1 << VTCR_EL2_VS_SHIFT)
 
+#define VTCR_EL2_T0SZ(x)	TCR_T0SZ(x)
+
 /*
  * We configure the Stage-2 page tables to always restrict the IPA space to be
  * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c
index 603e1ee83e89..e1ca672e937a 100644
--- a/arch/arm64/kvm/hyp/s2-setup.c
+++ b/arch/arm64/kvm/hyp/s2-setup.c
@@ -19,45 +19,27 @@
 #include <asm/kvm_arm.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_hyp.h>
+#include <asm/cpufeature.h>
 
 u32 __hyp_text __init_stage2_translation(void)
 {
 	u64 val = VTCR_EL2_FLAGS;
 	u64 parange;
+	u32 phys_shift;
 	u64 tmp;
 
 	/*
 	 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS
-	 * bits in VTCR_EL2. Amusingly, the PARange is 4 bits, while
-	 * PS is only 3. Fortunately, bit 19 is RES0 in VTCR_EL2...
+	 * bits in VTCR_EL2. Amusingly, the PARange is 4 bits, but the
+	 * allocated values are limited to 3bits.
 	 */
 	parange = read_sysreg(id_aa64mmfr0_el1) & 7;
 	if (parange > ID_AA64MMFR0_PARANGE_MAX)
 		parange = ID_AA64MMFR0_PARANGE_MAX;
-	val |= parange << 16;
+	val |= parange << VTCR_EL2_PS_SHIFT;
 
 	/* Compute the actual PARange... */
-	switch (parange) {
-	case 0:
-		parange = 32;
-		break;
-	case 1:
-		parange = 36;
-		break;
-	case 2:
-		parange = 40;
-		break;
-	case 3:
-		parange = 42;
-		break;
-	case 4:
-		parange = 44;
-		break;
-	case 5:
-	default:
-		parange = 48;
-		break;
-	}
+	phys_shift = id_aa64mmfr0_parange_to_phys_shift(parange);
 
 	/*
 	 * ... and clamp it to 40 bits, unless we have some braindead
@@ -65,7 +47,7 @@ u32 __hyp_text __init_stage2_translation(void)
 	 * return that value for the rest of the kernel to decide what
 	 * to do.
 	 */
-	val |= 64 - (parange > 40 ? 40 : parange);
+	val |= VTCR_EL2_T0SZ(phys_shift > 40 ? 40 : phys_shift);
 
 	/*
 	 * Check the availability of Hardware Access Flag / Dirty Bit
@@ -86,5 +68,5 @@ u32 __hyp_text __init_stage2_translation(void)
 
 	write_sysreg(val, vtcr_el2);
 
-	return parange;
+	return phys_shift;
 }
-- 
2.19.0


WARNING: multiple messages have this Message-ID (diff)
From: suzuki.poulose@arm.com (Suzuki K Poulose)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 05/18] kvm: arm64: Clean up VTCR_EL2 initialisation
Date: Mon, 17 Sep 2018 11:41:27 +0100	[thread overview]
Message-ID: <20180917104144.19188-6-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20180917104144.19188-1-suzuki.poulose@arm.com>

Use the new helper for converting the parange to the physical shift.
Also, add the missing definitions for the VTCR_EL2 register fields
and use them instead of hard coding numbers.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changs sinec v3
 - Update comment about reserved bits
 - Added Reviewed-by from Eric
---
 arch/arm64/include/asm/kvm_arm.h |  3 +++
 arch/arm64/kvm/hyp/s2-setup.c    | 34 ++++++++------------------------
 2 files changed, 11 insertions(+), 26 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index aa45df752a16..5f807b680a5f 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -107,6 +107,7 @@
 #define VTCR_EL2_RES1		(1 << 31)
 #define VTCR_EL2_HD		(1 << 22)
 #define VTCR_EL2_HA		(1 << 21)
+#define VTCR_EL2_PS_SHIFT	TCR_EL2_PS_SHIFT
 #define VTCR_EL2_PS_MASK	TCR_EL2_PS_MASK
 #define VTCR_EL2_TG0_MASK	TCR_TG0_MASK
 #define VTCR_EL2_TG0_4K		TCR_TG0_4K
@@ -127,6 +128,8 @@
 #define VTCR_EL2_VS_8BIT	(0 << VTCR_EL2_VS_SHIFT)
 #define VTCR_EL2_VS_16BIT	(1 << VTCR_EL2_VS_SHIFT)
 
+#define VTCR_EL2_T0SZ(x)	TCR_T0SZ(x)
+
 /*
  * We configure the Stage-2 page tables to always restrict the IPA space to be
  * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c
index 603e1ee83e89..e1ca672e937a 100644
--- a/arch/arm64/kvm/hyp/s2-setup.c
+++ b/arch/arm64/kvm/hyp/s2-setup.c
@@ -19,45 +19,27 @@
 #include <asm/kvm_arm.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_hyp.h>
+#include <asm/cpufeature.h>
 
 u32 __hyp_text __init_stage2_translation(void)
 {
 	u64 val = VTCR_EL2_FLAGS;
 	u64 parange;
+	u32 phys_shift;
 	u64 tmp;
 
 	/*
 	 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS
-	 * bits in VTCR_EL2. Amusingly, the PARange is 4 bits, while
-	 * PS is only 3. Fortunately, bit 19 is RES0 in VTCR_EL2...
+	 * bits in VTCR_EL2. Amusingly, the PARange is 4 bits, but the
+	 * allocated values are limited to 3bits.
 	 */
 	parange = read_sysreg(id_aa64mmfr0_el1) & 7;
 	if (parange > ID_AA64MMFR0_PARANGE_MAX)
 		parange = ID_AA64MMFR0_PARANGE_MAX;
-	val |= parange << 16;
+	val |= parange << VTCR_EL2_PS_SHIFT;
 
 	/* Compute the actual PARange... */
-	switch (parange) {
-	case 0:
-		parange = 32;
-		break;
-	case 1:
-		parange = 36;
-		break;
-	case 2:
-		parange = 40;
-		break;
-	case 3:
-		parange = 42;
-		break;
-	case 4:
-		parange = 44;
-		break;
-	case 5:
-	default:
-		parange = 48;
-		break;
-	}
+	phys_shift = id_aa64mmfr0_parange_to_phys_shift(parange);
 
 	/*
 	 * ... and clamp it to 40 bits, unless we have some braindead
@@ -65,7 +47,7 @@ u32 __hyp_text __init_stage2_translation(void)
 	 * return that value for the rest of the kernel to decide what
 	 * to do.
 	 */
-	val |= 64 - (parange > 40 ? 40 : parange);
+	val |= VTCR_EL2_T0SZ(phys_shift > 40 ? 40 : phys_shift);
 
 	/*
 	 * Check the availability of Hardware Access Flag / Dirty Bit
@@ -86,5 +68,5 @@ u32 __hyp_text __init_stage2_translation(void)
 
 	write_sysreg(val, vtcr_el2);
 
-	return parange;
+	return phys_shift;
 }
-- 
2.19.0

  parent reply	other threads:[~2018-09-17 10:42 UTC|newest]

Thread overview: 120+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-17 10:41 [PATCH v5 00/18] kvm: arm64: Dynamic IPA and 52bit IPA Suzuki K Poulose
2018-09-17 10:41 ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 01/18] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 02/18] kvm: arm/arm64: Remove spurious WARN_ON Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 03/18] kvm: arm64: Add helper for loading the stage2 setting for a VM Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 04/18] arm64: Add a helper for PARange to physical shift conversion Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` Suzuki K Poulose [this message]
2018-09-17 10:41   ` [PATCH v5 05/18] kvm: arm64: Clean up VTCR_EL2 initialisation Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 06/18] kvm: arm/arm64: Allow arch specific configurations for VM Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-20 10:22   ` Auger Eric
2018-09-20 10:22     ` Auger Eric
2018-09-20 10:22     ` Auger Eric
2018-09-17 10:41 ` [PATCH v5 07/18] kvm: arm64: Configure VTCR_EL2 per VM Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-20 10:21   ` Auger Eric
2018-09-20 10:21     ` Auger Eric
2018-09-20 10:38     ` Suzuki K Poulose
2018-09-20 10:38       ` Suzuki K Poulose
2018-09-20 10:38       ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 08/18] kvm: arm/arm64: Prepare for VM specific stage2 translations Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-20 14:07   ` Auger Eric
2018-09-20 14:07     ` Auger Eric
2018-09-20 14:07     ` Auger Eric
2018-09-17 10:41 ` [PATCH v5 09/18] kvm: arm64: Prepare for dynamic stage2 page table layout Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 10/18] kvm: arm64: Make stage2 page table layout dynamic Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-20 14:07   ` Auger Eric
2018-09-20 14:07     ` Auger Eric
2018-09-17 10:41 ` [PATCH v5 11/18] kvm: arm64: Dynamic configuration of VTTBR mask Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-20 14:07   ` Auger Eric
2018-09-20 14:07     ` Auger Eric
2018-09-20 15:22     ` Suzuki K Poulose
2018-09-20 15:22       ` Suzuki K Poulose
2018-09-20 15:22       ` Suzuki K Poulose
2018-09-25 11:56       ` Auger Eric
2018-09-25 11:56         ` Auger Eric
2018-09-17 10:41 ` [PATCH v5 12/18] kvm: arm64: Configure VTCR_EL2.SL0 per VM Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-20 14:25   ` Auger Eric
2018-09-20 14:25     ` Auger Eric
2018-09-20 15:25     ` Suzuki K Poulose
2018-09-20 15:25       ` Suzuki K Poulose
2018-09-20 15:25       ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 13/18] kvm: arm64: Switch to per VM IPA limit Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 14/18] vgic: Add support for 52bit guest physical address Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-21 14:57   ` Auger Eric
2018-09-21 14:57     ` Auger Eric
2018-09-25 10:49     ` Suzuki K Poulose
2018-09-25 10:49       ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 15/18] kvm: arm64: Add 52bit support for PAR to HPFAR conversoin Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-25  9:59   ` Auger Eric
2018-09-25  9:59     ` Auger Eric
2018-09-17 10:41 ` [PATCH v5 16/18] kvm: arm64: Set a limit on the IPA size Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-25  9:59   ` Auger Eric
2018-09-25  9:59     ` Auger Eric
2018-09-25  9:59     ` Auger Eric
2018-09-25 11:10     ` Suzuki K Poulose
2018-09-25 11:10       ` Suzuki K Poulose
2018-09-25 11:10       ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 17/18] kvm: arm64: Limit the minimum number of page table levels Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-25 10:00   ` Auger Eric
2018-09-25 10:00     ` Auger Eric
2018-09-25 10:25     ` Suzuki K Poulose
2018-09-25 10:25       ` Suzuki K Poulose
2018-09-17 10:41 ` [PATCH v5 18/18] kvm: arm64: Allow tuning the physical address size for VM Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 14:20   ` Peter Maydell
2018-09-17 14:20     ` Peter Maydell
2018-09-17 14:43     ` Suzuki K Poulose
2018-09-17 14:43       ` Suzuki K Poulose
2018-09-18  1:55   ` Peter Maydell
2018-09-18  1:55     ` Peter Maydell
2018-09-18  1:55     ` Peter Maydell
2018-09-18 15:16     ` Suzuki K Poulose
2018-09-18 15:16       ` Suzuki K Poulose
2018-09-18 15:36       ` Peter Maydell
2018-09-18 15:36         ` Peter Maydell
2018-09-18 16:27         ` Suzuki K Poulose
2018-09-18 16:27           ` Suzuki K Poulose
2018-09-18 16:27           ` Suzuki K Poulose
2018-09-18 17:15           ` Peter Maydell
2018-09-18 17:15             ` Peter Maydell
2018-09-19 10:03             ` Suzuki K Poulose
2018-09-19 10:03               ` Suzuki K Poulose
2018-09-19 10:03               ` Suzuki K Poulose
2018-09-25 10:00   ` Auger Eric
2018-09-25 10:00     ` Auger Eric
2018-09-25 10:24     ` Suzuki K Poulose
2018-09-25 10:24       ` Suzuki K Poulose
2018-09-25 10:24       ` Suzuki K Poulose
2018-09-17 10:41 ` [kvmtool PATCH v5 19/18] kvmtool: Allow backends to run checks on the KVM device fd Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` [kvmtool PATCH v5 20/18] kvmtool: arm64: Add support for guest physical address size Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` [kvmtool PATCH v5 21/18] kvmtool: arm64: Switch memory layout Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41 ` [kvmtool PATCH v5 22/18] kvmtool: arm: Add support for creating VM with PA size Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose
2018-09-17 10:41   ` Suzuki K Poulose

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