From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de, Alistair.Francis@wdc.com Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [Qemu-devel] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Date: Wed, 31 Oct 2018 14:19:55 +0100 [thread overview] Message-ID: <20181031132029.4887-2-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de> CPURISCVState is rarely used, so there is no need to pass it to every translate function. This paves the way for decodetree which only passes DisasContext to translate functions. Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/riscv/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d147..e81b9f097e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -52,6 +52,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + CPURISCVState *env; } DisasContext; /* convert riscv funct3 to qemu memop for load/store */ @@ -1789,19 +1790,19 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) } } -static void decode_opc(CPURISCVState *env, DisasContext *ctx) +static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ if (extract32(ctx->opcode, 0, 2) != 3) { - if (!riscv_has_ext(env, RVC)) { + if (!riscv_has_ext(ctx->env, RVC)) { gen_exception_illegal(ctx); } else { ctx->pc_succ_insn = ctx->base.pc_next + 2; - decode_RV32_64C(env, ctx); + decode_RV32_64C(ctx->env, ctx); } } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; - decode_RV32_64G(env, ctx); + decode_RV32_64G(ctx->env, ctx); } } @@ -1846,10 +1847,10 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - CPURISCVState *env = cpu->env_ptr; + ctx->env = cpu->env_ptr; - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); - decode_opc(env, ctx); + ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next); + decode_opc(ctx); ctx->base.pc_next = ctx->pc_succ_insn; if (ctx->base.is_jmp == DISAS_NEXT) { -- 2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de, Alistair.Francis@wdc.com Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Date: Wed, 31 Oct 2018 14:19:55 +0100 [thread overview] Message-ID: <20181031132029.4887-2-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de> CPURISCVState is rarely used, so there is no need to pass it to every translate function. This paves the way for decodetree which only passes DisasContext to translate functions. Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/riscv/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d147..e81b9f097e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -52,6 +52,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + CPURISCVState *env; } DisasContext; /* convert riscv funct3 to qemu memop for load/store */ @@ -1789,19 +1790,19 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) } } -static void decode_opc(CPURISCVState *env, DisasContext *ctx) +static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ if (extract32(ctx->opcode, 0, 2) != 3) { - if (!riscv_has_ext(env, RVC)) { + if (!riscv_has_ext(ctx->env, RVC)) { gen_exception_illegal(ctx); } else { ctx->pc_succ_insn = ctx->base.pc_next + 2; - decode_RV32_64C(env, ctx); + decode_RV32_64C(ctx->env, ctx); } } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; - decode_RV32_64G(env, ctx); + decode_RV32_64G(ctx->env, ctx); } } @@ -1846,10 +1847,10 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - CPURISCVState *env = cpu->env_ptr; + ctx->env = cpu->env_ptr; - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); - decode_opc(env, ctx); + ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next); + decode_opc(ctx); ctx->base.pc_next = ctx->pc_succ_insn; if (ctx->base.is_jmp == DISAS_NEXT) { -- 2.19.1
next prev parent reply other threads:[~2018-10-31 13:21 UTC|newest] Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-31 13:19 [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree Bastian Koppelmann 2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:19 ` Bastian Koppelmann [this message] 2018-10-31 13:19 ` [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann 2018-10-31 17:07 ` [Qemu-devel] " Richard Henderson 2018-10-31 17:07 ` [Qemu-riscv] " Richard Henderson 2018-10-31 20:14 ` [Qemu-devel] " Alistair Francis 2018-10-31 20:14 ` [Qemu-riscv] " Alistair Francis 2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann 2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 20:20 ` [Qemu-devel] " Alistair 2018-10-31 20:20 ` [Qemu-riscv] " Alistair 2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann 2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 17:11 ` [Qemu-devel] " Richard Henderson 2018-10-31 17:11 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann 2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 05/35] target/riscv: Convert RV64I " Bastian Koppelmann 2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 17:14 ` [Qemu-devel] " Richard Henderson 2018-10-31 17:14 ` [Qemu-riscv] " Richard Henderson 2018-10-31 20:26 ` [Qemu-devel] " Alistair 2018-10-31 20:26 ` [Qemu-riscv] " Alistair 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 17:15 ` [Qemu-devel] " Richard Henderson 2018-10-31 17:15 ` [Qemu-riscv] " Richard Henderson 2018-10-31 20:29 ` [Qemu-devel] " Alistair 2018-10-31 20:29 ` [Qemu-riscv] " Alistair 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 20:30 ` [Qemu-devel] " Alistair 2018-10-31 20:30 ` [Qemu-riscv] " Alistair 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 20:46 ` [Qemu-devel] " Alistair 2018-10-31 20:46 ` [Qemu-riscv] " Alistair 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 09/35] target/riscv: Convert RVXM " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 20:38 ` [Qemu-devel] " Alistair 2018-10-31 20:38 ` [Qemu-riscv] " Alistair 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 10/35] target/riscv: Convert RV32A " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 11/35] target/riscv: Convert RV64A " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 20:49 ` [Qemu-devel] " Alistair 2018-10-31 20:49 ` [Qemu-riscv] " Alistair 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 12/35] target/riscv: Convert RV32F " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 13/35] target/riscv: Convert RV64F " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 14/35] target/riscv: Convert RV32D " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 15/35] target/riscv: Convert RV64D " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 16/35] target/riscv: Convert RV priv " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 20:50 ` [Qemu-devel] " Alistair 2018-10-31 20:50 ` [Qemu-riscv] " Alistair 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:09 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:09 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:09 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:09 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:18 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:18 ` [Qemu-riscv] " Richard Henderson 2019-01-11 13:10 ` [Qemu-devel] " Bastian Koppelmann 2019-01-11 13:10 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-11 21:00 ` Richard Henderson 2019-01-11 21:00 ` [Qemu-riscv] " Richard Henderson 2019-01-18 12:00 ` Bastian Koppelmann 2019-01-18 12:00 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:26 ` Richard Henderson 2018-10-31 22:26 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 20:44 ` [Qemu-devel] " Alistair Francis 2018-10-31 20:44 ` [Qemu-riscv] " Alistair Francis 2018-10-31 22:27 ` Richard Henderson 2018-10-31 22:27 ` [Qemu-riscv] " Richard Henderson 2018-10-31 22:26 ` Richard Henderson 2018-10-31 22:26 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:38 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:38 ` [Qemu-riscv] " Richard Henderson 2018-11-01 15:59 ` [Qemu-devel] " Palmer Dabbelt 2018-11-01 15:59 ` [Qemu-riscv] " Palmer Dabbelt 2018-11-05 17:00 ` [Qemu-devel] " Bastian Koppelmann 2018-11-05 17:00 ` [Qemu-riscv] " Bastian Koppelmann 2018-11-07 0:56 ` Palmer Dabbelt 2018-11-07 0:56 ` [Qemu-riscv] " Palmer Dabbelt 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:39 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:39 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 29/35] target/riscv: Remove gen_system() Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:42 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:42 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:43 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:43 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:45 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:45 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:47 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:47 ` [Qemu-riscv] " Richard Henderson 2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann 2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann 2018-10-31 22:49 ` [Qemu-devel] " Richard Henderson 2018-10-31 22:49 ` [Qemu-riscv] " Richard Henderson 2018-11-02 8:48 ` [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree no-reply 2018-11-02 8:48 ` [Qemu-riscv] " no-reply
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