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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
	kbastian@mail.uni-paderborn.de, Alistair.Francis@wdc.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch()
Date: Wed, 31 Oct 2018 14:20:15 +0100	[thread overview]
Message-ID: <20181031132029.4887-22-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de>

We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
 target/riscv/insn_trans/trans_rvi.inc.c | 46 +++++++++++++++++-------
 target/riscv/translate.c                | 47 -------------------------
 2 files changed, 33 insertions(+), 60 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 4d090d68e7..4f63b904a3 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     return true;
 }
 
-static bool trans_beq(DisasContext *ctx, arg_beq *a)
+static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+    TCGLabel *l = gen_new_label();
+    TCGv source1, source2;
+    source1 = tcg_temp_new();
+    source2 = tcg_temp_new();
+    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(source2, a->rs2);
+
+    tcg_gen_brcond_tl(cond, source1, source2, l);
+    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+    gen_set_label(l); /* branch taken */
+
+    if (!riscv_has_ext(ctx->env, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+        /* misaligned */
+        gen_exception_inst_addr_mis(ctx);
+    } else {
+        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+    }
+    ctx->base.is_jmp = DISAS_NORETURN;
+
+    tcg_temp_free(source1);
+    tcg_temp_free(source2);
+
     return true;
 }
 
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+    return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
 static bool trans_bne(DisasContext *ctx, arg_bne *a)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_NE);
 }
 
 static bool trans_blt(DisasContext *ctx, arg_blt *a)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_LT);
 }
 
 static bool trans_bge(DisasContext *ctx, arg_bge *a)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_GE);
 }
 
 static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_LTU);
 }
 
 static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 {
-
-    gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_GEU);
 }
 
 static bool trans_lb(DisasContext *ctx, arg_lb *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b78e423d94..585378d1e1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,53 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
-                       int rs1, int rs2, target_long bimm)
-{
-    TCGLabel *l = gen_new_label();
-    TCGv source1, source2;
-    source1 = tcg_temp_new();
-    source2 = tcg_temp_new();
-    gen_get_gpr(source1, rs1);
-    gen_get_gpr(source2, rs2);
-
-    switch (opc) {
-    case OPC_RISC_BEQ:
-        tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
-        break;
-    case OPC_RISC_BNE:
-        tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
-        break;
-    case OPC_RISC_BLT:
-        tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
-        break;
-    case OPC_RISC_BGE:
-        tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
-        break;
-    case OPC_RISC_BLTU:
-        tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
-        break;
-    case OPC_RISC_BGEU:
-        tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
-        break;
-    default:
-        gen_exception_illegal(ctx);
-        return;
-    }
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-
-    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
-    gen_set_label(l); /* branch taken */
-    if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
-        /* misaligned */
-        gen_exception_inst_addr_mis(ctx);
-    } else {
-        gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
-    }
-    ctx->base.is_jmp = DISAS_NORETURN;
-}
-
 static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
         target_long imm)
 {
-- 
2.19.1

WARNING: multiple messages have this Message-ID (diff)
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
	kbastian@mail.uni-paderborn.de, Alistair.Francis@wdc.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-riscv] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch()
Date: Wed, 31 Oct 2018 14:20:15 +0100	[thread overview]
Message-ID: <20181031132029.4887-22-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de>

We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
 target/riscv/insn_trans/trans_rvi.inc.c | 46 +++++++++++++++++-------
 target/riscv/translate.c                | 47 -------------------------
 2 files changed, 33 insertions(+), 60 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 4d090d68e7..4f63b904a3 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     return true;
 }
 
-static bool trans_beq(DisasContext *ctx, arg_beq *a)
+static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+    TCGLabel *l = gen_new_label();
+    TCGv source1, source2;
+    source1 = tcg_temp_new();
+    source2 = tcg_temp_new();
+    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(source2, a->rs2);
+
+    tcg_gen_brcond_tl(cond, source1, source2, l);
+    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+    gen_set_label(l); /* branch taken */
+
+    if (!riscv_has_ext(ctx->env, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+        /* misaligned */
+        gen_exception_inst_addr_mis(ctx);
+    } else {
+        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+    }
+    ctx->base.is_jmp = DISAS_NORETURN;
+
+    tcg_temp_free(source1);
+    tcg_temp_free(source2);
+
     return true;
 }
 
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+    return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
 static bool trans_bne(DisasContext *ctx, arg_bne *a)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_NE);
 }
 
 static bool trans_blt(DisasContext *ctx, arg_blt *a)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_LT);
 }
 
 static bool trans_bge(DisasContext *ctx, arg_bge *a)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_GE);
 }
 
 static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
 {
-    gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_LTU);
 }
 
 static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 {
-
-    gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
-    return true;
+    return gen_branch(ctx, a, TCG_COND_GEU);
 }
 
 static bool trans_lb(DisasContext *ctx, arg_lb *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b78e423d94..585378d1e1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,53 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
-                       int rs1, int rs2, target_long bimm)
-{
-    TCGLabel *l = gen_new_label();
-    TCGv source1, source2;
-    source1 = tcg_temp_new();
-    source2 = tcg_temp_new();
-    gen_get_gpr(source1, rs1);
-    gen_get_gpr(source2, rs2);
-
-    switch (opc) {
-    case OPC_RISC_BEQ:
-        tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
-        break;
-    case OPC_RISC_BNE:
-        tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
-        break;
-    case OPC_RISC_BLT:
-        tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
-        break;
-    case OPC_RISC_BGE:
-        tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
-        break;
-    case OPC_RISC_BLTU:
-        tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
-        break;
-    case OPC_RISC_BGEU:
-        tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
-        break;
-    default:
-        gen_exception_illegal(ctx);
-        return;
-    }
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-
-    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
-    gen_set_label(l); /* branch taken */
-    if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
-        /* misaligned */
-        gen_exception_inst_addr_mis(ctx);
-    } else {
-        gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
-    }
-    ctx->base.is_jmp = DISAS_NORETURN;
-}
-
 static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
         target_long imm)
 {
-- 
2.19.1



  parent reply	other threads:[~2018-10-31 13:21 UTC|newest]

Thread overview: 140+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-31 13:19 [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2018-10-31 13:19   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 17:07   ` [Qemu-devel] " Richard Henderson
2018-10-31 17:07     ` [Qemu-riscv] " Richard Henderson
2018-10-31 20:14   ` [Qemu-devel] " Alistair Francis
2018-10-31 20:14     ` [Qemu-riscv] " Alistair Francis
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-31 13:19   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:20   ` [Qemu-devel] " Alistair
2018-10-31 20:20     ` [Qemu-riscv] " Alistair
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-31 13:19   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 17:11   ` [Qemu-devel] " Richard Henderson
2018-10-31 17:11     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2018-10-31 13:19   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2018-10-31 13:19   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 17:14   ` [Qemu-devel] " Richard Henderson
2018-10-31 17:14     ` [Qemu-riscv] " Richard Henderson
2018-10-31 20:26   ` [Qemu-devel] " Alistair
2018-10-31 20:26     ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 17:15   ` [Qemu-devel] " Richard Henderson
2018-10-31 17:15     ` [Qemu-riscv] " Richard Henderson
2018-10-31 20:29   ` [Qemu-devel] " Alistair
2018-10-31 20:29     ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:30   ` [Qemu-devel] " Alistair
2018-10-31 20:30     ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:46   ` [Qemu-devel] " Alistair
2018-10-31 20:46     ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:38   ` [Qemu-devel] " Alistair
2018-10-31 20:38     ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:49   ` [Qemu-devel] " Alistair
2018-10-31 20:49     ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:50   ` [Qemu-devel] " Alistair
2018-10-31 20:50     ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` Bastian Koppelmann [this message]
2018-10-31 13:20   ` [Qemu-riscv] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:09   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:09     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:09   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:09     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:18   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:18     ` [Qemu-riscv] " Richard Henderson
2019-01-11 13:10     ` [Qemu-devel] " Bastian Koppelmann
2019-01-11 13:10       ` [Qemu-riscv] " Bastian Koppelmann
2019-01-11 21:00       ` Richard Henderson
2019-01-11 21:00         ` [Qemu-riscv] " Richard Henderson
2019-01-18 12:00         ` Bastian Koppelmann
2019-01-18 12:00           ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:26   ` Richard Henderson
2018-10-31 22:26     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:44   ` [Qemu-devel] " Alistair Francis
2018-10-31 20:44     ` [Qemu-riscv] " Alistair Francis
2018-10-31 22:27     ` Richard Henderson
2018-10-31 22:27       ` [Qemu-riscv] " Richard Henderson
2018-10-31 22:26   ` Richard Henderson
2018-10-31 22:26     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:38   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:38     ` [Qemu-riscv] " Richard Henderson
2018-11-01 15:59     ` [Qemu-devel] " Palmer Dabbelt
2018-11-01 15:59       ` [Qemu-riscv] " Palmer Dabbelt
2018-11-05 17:00       ` [Qemu-devel] " Bastian Koppelmann
2018-11-05 17:00         ` [Qemu-riscv] " Bastian Koppelmann
2018-11-07  0:56         ` Palmer Dabbelt
2018-11-07  0:56           ` [Qemu-riscv] " Palmer Dabbelt
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:39   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:39     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:42   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:42     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:43   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:43     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:45   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:45     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:47   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:47     ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2018-10-31 13:20   ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:49   ` [Qemu-devel] " Richard Henderson
2018-10-31 22:49     ` [Qemu-riscv] " Richard Henderson
2018-11-02  8:48 ` [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree no-reply
2018-11-02  8:48   ` [Qemu-riscv] " no-reply

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