From: "Z.q. Hou" <zhiqiang.hou@nxp.com> To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "bhelgaas@google.com" <bhelgaas@google.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>, "shawnguo@kernel.org" <shawnguo@kernel.org>, Leo Li <leoyang.li@nxp.com>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com> Cc: Mingkai Hu <mingkai.hu@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>, "Z.q. Hou" <zhiqiang.hou@nxp.com> Subject: [PATCH 11/23] PCI: mobiveil: only fixup the Class Code field Date: Tue, 6 Nov 2018 13:20:16 +0000 [thread overview] Message-ID: <20181106131807.29951-12-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20181106131807.29951-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Fixup the Class Code to PCI bridge, do not change the Revision ID. And move the fixup to *_host_init function. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- drivers/pci/controller/pcie-mobiveil.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 884c9f95374d..8e3630359597 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -652,6 +652,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) type, resource_size(win->res)); } + /* fixup for PCIe class register */ + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); + value &= 0xff; + value |= (PCI_CLASS_BRIDGE_PCI << 16); + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); + /* setup MSI hardware registers */ mobiveil_pcie_enable_msi(pcie); @@ -895,9 +901,6 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) goto error; } - /* fixup for PCIe class register */ - csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS); - /* initialize the IRQ domains */ ret = mobiveil_pcie_init_irq_domain(pcie); if (ret) { -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: zhiqiang.hou@nxp.com (Z.q. Hou) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 11/23] PCI: mobiveil: only fixup the Class Code field Date: Tue, 6 Nov 2018 13:20:16 +0000 [thread overview] Message-ID: <20181106131807.29951-12-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20181106131807.29951-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Fixup the Class Code to PCI bridge, do not change the Revision ID. And move the fixup to *_host_init function. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- drivers/pci/controller/pcie-mobiveil.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 884c9f95374d..8e3630359597 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -652,6 +652,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) type, resource_size(win->res)); } + /* fixup for PCIe class register */ + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); + value &= 0xff; + value |= (PCI_CLASS_BRIDGE_PCI << 16); + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); + /* setup MSI hardware registers */ mobiveil_pcie_enable_msi(pcie); @@ -895,9 +901,6 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) goto error; } - /* fixup for PCIe class register */ - csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS); - /* initialize the IRQ domains */ ret = mobiveil_pcie_init_irq_domain(pcie); if (ret) { -- 2.17.1
next prev parent reply other threads:[~2018-11-06 13:20 UTC|newest] Thread overview: 103+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-06 13:19 [PATCH 00/23] PCI: refactor the Mobiveil driver and add PCIe support for NXP LX SoCs Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` [PATCH 01/23] PCI: mobiveil: uniform the register accessors Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` [PATCH 02/23] PCI: mobiveil: format the code without function change Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` [PATCH 03/23] PCI: mobiveil: correct the returned error number Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` [PATCH 04/23] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` [PATCH 05/23] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` [PATCH 06/23] PCI: mobiveil: replace the resource list iteration function Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` [PATCH 07/23] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` [PATCH 08/23] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:19 ` Z.q. Hou 2018-11-06 13:20 ` [PATCH 09/23] PCI: mobiveil: correct the inbound/outbound window setup routine Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` [PATCH 10/23] PCI: mobiveil: fix the INTx process error Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-15 2:59 ` Z.q. Hou 2018-11-15 2:59 ` Z.q. Hou 2018-11-15 2:59 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou [this message] 2018-11-06 13:20 ` [PATCH 11/23] PCI: mobiveil: only fixup the Class Code field Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` [PATCH 12/23] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` [PATCH 13/23] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` [PATCH 14/23] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` [PATCH 15/23] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-12 18:12 ` Rob Herring 2018-11-12 18:12 ` Rob Herring 2018-11-13 6:08 ` Z.q. Hou 2018-11-13 6:08 ` Z.q. Hou 2018-11-13 6:08 ` Z.q. Hou 2018-11-14 9:33 ` Subrahmanya Lingappa 2018-11-14 9:33 ` Subrahmanya Lingappa 2018-11-15 2:27 ` Z.q. Hou 2018-11-15 2:27 ` Z.q. Hou 2018-11-15 2:27 ` Z.q. Hou 2018-11-06 13:20 ` [PATCH 16/23] PCI: mobiveil: refactor the Mobiveil driver Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` [PATCH 17/23] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:20 ` Z.q. Hou 2018-11-06 13:21 ` [PATCH 18/23] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` [PATCH 19/23] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` [PATCH 20/23] PCI: mobiveil: change prototype of function mobiveil_host_init Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe controller Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-08 21:29 ` Leo Li 2018-11-08 21:29 ` Leo Li 2018-11-08 21:29 ` Leo Li 2018-11-12 1:48 ` Z.q. Hou 2018-11-12 1:48 ` Z.q. Hou 2018-11-12 1:48 ` Z.q. Hou 2018-11-14 18:51 ` Leo Li 2018-11-14 18:51 ` Leo Li 2018-11-14 18:51 ` Leo Li 2018-11-15 2:47 ` Z.q. Hou 2018-11-15 2:47 ` Z.q. Hou 2018-11-15 2:47 ` Z.q. Hou 2018-11-06 13:21 ` [PATCH 22/23] PCI: mobiveil: add PCIe RC driver for NXP LX series SoCs Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` [PATCH 23/23] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-11-06 13:21 ` Z.q. Hou 2018-12-03 11:58 ` [PATCH 00/23] PCI: refactor the Mobiveil driver and add PCIe support for NXP LX SoCs Lorenzo Pieralisi 2018-12-03 11:58 ` Lorenzo Pieralisi 2018-12-03 11:58 ` Lorenzo Pieralisi 2018-12-10 10:13 ` Subrahmanya Lingappa 2018-12-10 10:16 ` Subrahmanya Lingappa 2018-12-10 10:16 ` Subrahmanya Lingappa
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