From: Vinod Koul <vkoul@kernel.org> To: Andy Gross <andy.gross@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Vinod Koul <vkoul@kernel.org> Subject: [PATCH v5 01/18] arm64: dts: qcom: qcs404: add base dts files Date: Fri, 9 Nov 2018 15:14:00 +0530 [thread overview] Message-ID: <20181109094417.12109-2-vkoul@kernel.org> (raw) In-Reply-To: <20181109094417.12109-1-vkoul@kernel.org> Add base dts files for QCS404 chipset along with cpu, timer, gcc and uart2 nodes. Signed-off-by: Vinod Koul <vkoul@kernel.org> --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 175 +++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi new file mode 100644 index 000000000000..91abcdc78505 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-qcs404.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; + assigned-clock-rates = <19200000>; + }; + + blsp1_uart2: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "okay"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b128000 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 0xff08>, + <GIC_PPI 3 0xff08>, + <GIC_PPI 4 0xff08>, + <GIC_PPI 1 0xff08>; + }; +}; -- 2.14.4
WARNING: multiple messages have this Message-ID (diff)
From: vkoul@kernel.org (Vinod Koul) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 01/18] arm64: dts: qcom: qcs404: add base dts files Date: Fri, 9 Nov 2018 15:14:00 +0530 [thread overview] Message-ID: <20181109094417.12109-2-vkoul@kernel.org> (raw) In-Reply-To: <20181109094417.12109-1-vkoul@kernel.org> Add base dts files for QCS404 chipset along with cpu, timer, gcc and uart2 nodes. Signed-off-by: Vinod Koul <vkoul@kernel.org> --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 175 +++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi new file mode 100644 index 000000000000..91abcdc78505 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-qcs404.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu at 100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu at 101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu at 102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu at 103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory at 80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc at 0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller at 1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; + assigned-clock-rates = <19200000>; + }; + + blsp1_uart2: serial at 78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "okay"; + }; + + intc: interrupt-controller at b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + timer at b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + clock-frequency = <19200000>; + + frame at b121000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame at b123000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b123000 0x1000>; + status = "disabled"; + }; + + frame at b124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame at b125000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b125000 0x1000>; + status = "disabled"; + }; + + frame at b126000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b126000 0x1000>; + status = "disabled"; + }; + + frame at b127000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame at b128000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b128000 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 0xff08>, + <GIC_PPI 3 0xff08>, + <GIC_PPI 4 0xff08>, + <GIC_PPI 1 0xff08>; + }; +}; -- 2.14.4
next prev parent reply other threads:[~2018-11-09 9:44 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-09 9:43 [PATCH v5 00/18] arm64: dts: qcom: qcs404: Add Device tree nodes Vinod Koul 2018-11-09 9:43 ` Vinod Koul 2018-11-09 9:44 ` Vinod Koul [this message] 2018-11-09 9:44 ` [PATCH v5 01/18] arm64: dts: qcom: qcs404: add base dts files Vinod Koul 2018-11-17 23:10 ` Bjorn Andersson 2018-11-17 23:10 ` Bjorn Andersson 2018-11-09 9:44 ` [PATCH v5 02/18] arm64: dts: qcom: qcs404-evb: add dts files for EVBs Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-17 23:11 ` Bjorn Andersson 2018-11-17 23:11 ` Bjorn Andersson 2018-11-19 12:01 ` Amit Kucheria 2018-11-19 12:01 ` Amit Kucheria 2018-11-09 9:44 ` [PATCH v5 03/18] arm64: dts: qcom: qcs404: Add reserved-memory regions Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 04/18] arm64: dts: qcom: qcs404: Add RPM GLINK related nodes Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 05/18] arm64: dts: qcom: qcs404: Add PMS405 RPM regulators Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 06/18] arm64: dts: qcom: qcs404: add smp2p nodes Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 07/18] arm64: dts: qcom: qcs404: Add TLMM pinctrl node Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 08/18] arm64: dts: qcom: qcs404: Add sdcc1 node Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 09/18] arm64: dts: qcom: pms405: add spmi node Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 10/18] arm64: dts: qcom: qcs404: " Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 11/18] arm64: dts: qcom: pms405: add rtc node Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 12/18] arm64: dts: qcom: pms405: add gpios Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-17 23:12 ` Bjorn Andersson 2018-11-17 23:12 ` Bjorn Andersson 2018-11-09 9:44 ` [PATCH v5 13/18] arm64: dts: qcom: qcs404: Add scm firmware node Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 14/18] arm64: dts: qcom: qcs404: Add remoteproc nodes Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-19 5:31 ` Sibi Sankar 2018-11-19 5:31 ` Sibi Sankar 2018-11-09 9:44 ` [PATCH v5 15/18] arm64: dts: qcom: qcs404: add prng-ee node Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 16/18] arm64: dts: qcom: qcs404: Add BAM DMA node Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 17/18] arm64: dts: qcom: qcs404: Use BAM DMA for serial uart2 Vinod Koul 2018-11-09 9:44 ` Vinod Koul 2018-11-09 9:44 ` [PATCH v5 18/18] arm64: dts: qcom: pms405: Add pon and pwrkey nodes Vinod Koul 2018-11-09 9:44 ` Vinod Koul
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