From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Joseph Lo <josephl@nvidia.com>
Subject: [PATCH V2 20/21] arm64: dts: tegra210-smaug: enable DFLL clock
Date: Thu, 13 Dec 2018 17:34:37 +0800 [thread overview]
Message-ID: <20181213093438.29621-21-josephl@nvidia.com> (raw)
In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com>
Enable DFLL clock for Smaug board.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
*V2:
- add ack tag
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 79cfcd5b7e62..c08c5471b974 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1698,6 +1698,18 @@
status = "okay";
};
+ clock@70110000 {
+ status = "okay";
+ nvidia,cf = <6>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,i2c-fs-rate = <400000>;
+ nvidia,sample-rate = <12500>;
+ vdd-cpu-supply = <&max77621_cpu>;
+ };
+
aconnect@702c0000 {
status = "okay";
--
2.19.2
WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
Joseph Lo <josephl@nvidia.com>
Subject: [PATCH V2 20/21] arm64: dts: tegra210-smaug: enable DFLL clock
Date: Thu, 13 Dec 2018 17:34:37 +0800 [thread overview]
Message-ID: <20181213093438.29621-21-josephl@nvidia.com> (raw)
In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com>
Enable DFLL clock for Smaug board.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
*V2:
- add ack tag
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 79cfcd5b7e62..c08c5471b974 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1698,6 +1698,18 @@
status = "okay";
};
+ clock@70110000 {
+ status = "okay";
+ nvidia,cf = <6>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,i2c-fs-rate = <400000>;
+ nvidia,sample-rate = <12500>;
+ vdd-cpu-supply = <&max77621_cpu>;
+ };
+
aconnect@702c0000 {
status = "okay";
--
2.19.2
WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Joseph Lo <josephl@nvidia.com>
Subject: [PATCH V2 20/21] arm64: dts: tegra210-smaug: enable DFLL clock
Date: Thu, 13 Dec 2018 17:34:37 +0800 [thread overview]
Message-ID: <20181213093438.29621-21-josephl@nvidia.com> (raw)
In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com>
Enable DFLL clock for Smaug board.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
*V2:
- add ack tag
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 79cfcd5b7e62..c08c5471b974 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1698,6 +1698,18 @@
status = "okay";
};
+ clock@70110000 {
+ status = "okay";
+ nvidia,cf = <6>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,i2c-fs-rate = <400000>;
+ nvidia,sample-rate = <12500>;
+ vdd-cpu-supply = <&max77621_cpu>;
+ };
+
aconnect@702c0000 {
status = "okay";
--
2.19.2
_______________________________________________
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next prev parent reply other threads:[~2018-12-13 9:34 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-13 9:34 [PATCH V2 00/21] Tegra210 DFLL support Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 01/21] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 02/21] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 03/21] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 04/21] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 05/21] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 06/21] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 11:18 ` Jon Hunter
2018-12-13 11:18 ` Jon Hunter
2018-12-13 11:18 ` Jon Hunter
2018-12-14 7:08 ` Joseph Lo
2018-12-14 7:08 ` Joseph Lo
2018-12-14 7:08 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 07/21] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 11:41 ` Jon Hunter
2018-12-13 11:41 ` Jon Hunter
2018-12-13 11:41 ` Jon Hunter
2018-12-14 7:11 ` Joseph Lo
2018-12-14 7:11 ` Joseph Lo
2018-12-14 7:11 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 08/21] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 11:46 ` Jon Hunter
2018-12-13 11:46 ` Jon Hunter
2018-12-13 11:46 ` Jon Hunter
2018-12-14 7:18 ` Joseph Lo
2018-12-14 7:18 ` Joseph Lo
2018-12-14 7:18 ` Joseph Lo
2018-12-14 10:00 ` Jon Hunter
2018-12-14 10:00 ` Jon Hunter
2018-12-14 10:00 ` Jon Hunter
2018-12-13 9:34 ` [PATCH V2 09/21] clk: tegra: dfll: add protection for find_vdd_map APIs Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 12:46 ` Jon Hunter
2018-12-13 12:46 ` Jon Hunter
2018-12-13 12:46 ` Jon Hunter
2018-12-14 7:42 ` Joseph Lo
2018-12-14 7:42 ` Joseph Lo
2018-12-14 7:42 ` Joseph Lo
2018-12-17 11:38 ` Peter De Schrijver
2018-12-17 11:38 ` Peter De Schrijver
2018-12-17 11:38 ` Peter De Schrijver
2018-12-13 9:34 ` [PATCH V2 10/21] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 12:50 ` Jon Hunter
2018-12-13 12:50 ` Jon Hunter
2018-12-13 12:50 ` Jon Hunter
2018-12-14 7:43 ` Joseph Lo
2018-12-14 7:43 ` Joseph Lo
2018-12-14 7:43 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 11/21] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 12/21] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 10:49 ` Rafael J. Wysocki
2018-12-13 10:49 ` Rafael J. Wysocki
2018-12-13 10:49 ` Rafael J. Wysocki
2018-12-13 12:55 ` Jon Hunter
2018-12-13 12:55 ` Jon Hunter
2018-12-13 12:55 ` Jon Hunter
2018-12-18 5:34 ` Viresh Kumar
2018-12-18 5:34 ` Viresh Kumar
2018-12-18 5:34 ` Viresh Kumar
2018-12-13 9:34 ` [PATCH V2 13/21] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 14/21] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 13:09 ` Jon Hunter
2018-12-13 13:09 ` Jon Hunter
2018-12-13 13:09 ` Jon Hunter
2018-12-18 5:33 ` Viresh Kumar
2018-12-18 5:33 ` Viresh Kumar
2018-12-18 5:33 ` Viresh Kumar
2018-12-13 9:34 ` [PATCH V2 15/21] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 16/21] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 17/21] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 18/21] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 13:11 ` Jon Hunter
2018-12-13 13:11 ` Jon Hunter
2018-12-13 13:11 ` Jon Hunter
2018-12-13 9:34 ` [PATCH V2 19/21] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo [this message]
2018-12-13 9:34 ` [PATCH V2 20/21] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 21/21] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
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