[PATCH] drm/i915/icl: Fix clockgating issue when using scalars

[Radhakrishna Sripada <radhakrishna.sripada@intel.com>]

Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 61acbaf2af75..97344cca89c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5193,9 +5193,17 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 static void skylake_scaler_disable(struct intel_crtc *crtc)
 {
 	int i;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	i915_reg_t reg = CLKGATE_DIS_PSL(crtc->pipe);
 
 	for (i = 0; i < crtc->num_scalers; i++)
 		skl_detach_scaler(crtc, i);
+
+	/*
+	 * Wa_2006604312:icl
+	 */
+	if (IS_ICELAKE(dev_priv))
+		I915_WRITE(reg, I915_READ(reg) & ~DPFR_GATING_DIS);
 }
 
 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -5205,6 +5213,7 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	const struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
+	i915_reg_t reg = CLKGATE_DIS_PSL(pipe);
 
 	if (crtc_state->pch_pfit.enabled) {
 		u16 uv_rgb_hphase, uv_rgb_vphase;
@@ -5232,6 +5241,12 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
 			      PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
 		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
+
+		/*
+		 * Wa_2006604312:icl
+		*/
+		if (IS_ICELAKE(dev_priv))
+			I915_WRITE(reg, I915_READ(reg) | DPFR_GATING_DIS);
 	}
 }
 
@@ -5972,7 +5987,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
 	psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
-			 pipe_config->pch_pfit.enabled;
+			  pipe_config->pch_pfit.enabled;
 	if (psl_clkgate_wa)
 		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
 
-- 
2.20.0.rc2.7.g965798d1f299

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