From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
kthota@nvidia.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
linux-tegra@vger.kernel.org, vidyas@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V7 00/15] Add Tegra194 PCIe support
Date: Fri, 17 May 2019 18:08:31 +0530 [thread overview]
Message-ID: <20190517123846.3708-1-vidyas@nvidia.com> (raw)
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe
controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe
core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used
to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks)
to PCIe controller
This patch series
- Adds support for P2U PHY driver
- Adds support for PCIe host controller
- Adds device tree nodes each PCIe controllers
- Enables nodes applicable to p2972-0000 platform
- Adds helper APIs in Designware core driver to get capability regs offset
- Adds defines for new feature registers of PCIe spec revision 4
- Makes changes in DesignWare core driver to get Tegra194 PCIe working
Testing done on P2972-0000 platform
- Able to get PCIe link up with on-board Marvel eSATA controller
- Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot
- Able to do data transfers with both SATA drives and NVMe cards
Note
- Enabling x8 slot on P2972-0000 platform requires pinmux driver for Tegra194.
It is being worked on currently and hence Controller:5 (i.e. x8 slot) is
disabled in this patch series. A future patch series would enable this.
- This series is based on top of the following series
Jisheng's patches to add support to .remove() in Designware sub-system
https://patchwork.kernel.org/project/linux-pci/list/?series=98559
(Jisheng's patches are now accepted and applied for v5.2)
My patches made on top of Jisheng's patches to export various symbols
https://patchwork.kernel.org/project/linux-pci/list/?series=101259
Changes since [v6]:
* Took care of review comments from Rob
* Added a quirk to disable MSI for root ports
* Removed using pcie_pme_disable_msi() API in host controller driver
Changes since [v5]:
* Removed patch that exports pcie_bus_config symbol
* Took care of review comments from Thierry and Rob
Changes since [v4]:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
to pcie-designware.c file based on Bjorn's review comments
Changes since [v3]:
* Rebased on top of linux-next top of the tree
* Addressed Gustavo's comments and added his Ack for some of the changes.
Changes since [v2]:
* Addressed review comments from Thierry
Changes since [v1]:
* Addressed review comments from Bjorn, Thierry, Jonathan, Rob & Kishon
* Added more patches in v2 series
Vidya Sagar (15):
PCI: Add #defines for some of PCIe spec r4.0 features
PCI: Disable MSI for Tegra194 root port
PCI: dwc: Perform dbi regs write lock towards the end
PCI: dwc: Move config space capability search API
PCI: dwc: Add ext config space capability search API
dt-bindings: PCI: designware: Add binding for CDM register check
PCI: dwc: Add support to enable CDM register check
dt-bindings: Add PCIe supports-clkreq property
dt-bindings: PCI: tegra: Add device tree support for Tegra194
dt-bindings: PHY: P2U: Add Tegra194 P2U block
arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
arm64: tegra: Enable PCIe slots in P2972-0000 board
phy: tegra: Add PCIe PIPE2UPHY support
PCI: tegra: Add Tegra194 PCIe support
arm64: Add Tegra194 PCIe driver to defconfig
.../bindings/pci/designware-pcie.txt | 5 +
.../bindings/pci/nvidia,tegra194-pcie.txt | 158 ++
Documentation/devicetree/bindings/pci/pci.txt | 5 +
.../bindings/phy/phy-tegra194-p2u.txt | 28 +
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
.../boot/dts/nvidia/tegra194-p2972-0000.dts | 41 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 437 +++++
arch/arm64/configs/defconfig | 1 +
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
.../pci/controller/dwc/pcie-designware-ep.c | 37 +-
.../pci/controller/dwc/pcie-designware-host.c | 14 +-
drivers/pci/controller/dwc/pcie-designware.c | 88 +
drivers/pci/controller/dwc/pcie-designware.h | 12 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1620 +++++++++++++++++
drivers/pci/quirks.c | 14 +
drivers/phy/tegra/Kconfig | 7 +
drivers/phy/tegra/Makefile | 1 +
drivers/phy/tegra/pcie-p2u-tegra194.c | 109 ++
include/uapi/linux/pci_regs.h | 22 +-
20 files changed, 2569 insertions(+), 43 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
create mode 100644 drivers/phy/tegra/pcie-p2u-tegra194.c
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V7 00/15] Add Tegra194 PCIe support
Date: Fri, 17 May 2019 18:08:31 +0530 [thread overview]
Message-ID: <20190517123846.3708-1-vidyas@nvidia.com> (raw)
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe
controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe
core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used
to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks)
to PCIe controller
This patch series
- Adds support for P2U PHY driver
- Adds support for PCIe host controller
- Adds device tree nodes each PCIe controllers
- Enables nodes applicable to p2972-0000 platform
- Adds helper APIs in Designware core driver to get capability regs offset
- Adds defines for new feature registers of PCIe spec revision 4
- Makes changes in DesignWare core driver to get Tegra194 PCIe working
Testing done on P2972-0000 platform
- Able to get PCIe link up with on-board Marvel eSATA controller
- Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot
- Able to do data transfers with both SATA drives and NVMe cards
Note
- Enabling x8 slot on P2972-0000 platform requires pinmux driver for Tegra194.
It is being worked on currently and hence Controller:5 (i.e. x8 slot) is
disabled in this patch series. A future patch series would enable this.
- This series is based on top of the following series
Jisheng's patches to add support to .remove() in Designware sub-system
https://patchwork.kernel.org/project/linux-pci/list/?series=98559
(Jisheng's patches are now accepted and applied for v5.2)
My patches made on top of Jisheng's patches to export various symbols
https://patchwork.kernel.org/project/linux-pci/list/?series=101259
Changes since [v6]:
* Took care of review comments from Rob
* Added a quirk to disable MSI for root ports
* Removed using pcie_pme_disable_msi() API in host controller driver
Changes since [v5]:
* Removed patch that exports pcie_bus_config symbol
* Took care of review comments from Thierry and Rob
Changes since [v4]:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
to pcie-designware.c file based on Bjorn's review comments
Changes since [v3]:
* Rebased on top of linux-next top of the tree
* Addressed Gustavo's comments and added his Ack for some of the changes.
Changes since [v2]:
* Addressed review comments from Thierry
Changes since [v1]:
* Addressed review comments from Bjorn, Thierry, Jonathan, Rob & Kishon
* Added more patches in v2 series
Vidya Sagar (15):
PCI: Add #defines for some of PCIe spec r4.0 features
PCI: Disable MSI for Tegra194 root port
PCI: dwc: Perform dbi regs write lock towards the end
PCI: dwc: Move config space capability search API
PCI: dwc: Add ext config space capability search API
dt-bindings: PCI: designware: Add binding for CDM register check
PCI: dwc: Add support to enable CDM register check
dt-bindings: Add PCIe supports-clkreq property
dt-bindings: PCI: tegra: Add device tree support for Tegra194
dt-bindings: PHY: P2U: Add Tegra194 P2U block
arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
arm64: tegra: Enable PCIe slots in P2972-0000 board
phy: tegra: Add PCIe PIPE2UPHY support
PCI: tegra: Add Tegra194 PCIe support
arm64: Add Tegra194 PCIe driver to defconfig
.../bindings/pci/designware-pcie.txt | 5 +
.../bindings/pci/nvidia,tegra194-pcie.txt | 158 ++
Documentation/devicetree/bindings/pci/pci.txt | 5 +
.../bindings/phy/phy-tegra194-p2u.txt | 28 +
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
.../boot/dts/nvidia/tegra194-p2972-0000.dts | 41 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 437 +++++
arch/arm64/configs/defconfig | 1 +
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
.../pci/controller/dwc/pcie-designware-ep.c | 37 +-
.../pci/controller/dwc/pcie-designware-host.c | 14 +-
drivers/pci/controller/dwc/pcie-designware.c | 88 +
drivers/pci/controller/dwc/pcie-designware.h | 12 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1620 +++++++++++++++++
drivers/pci/quirks.c | 14 +
drivers/phy/tegra/Kconfig | 7 +
drivers/phy/tegra/Makefile | 1 +
drivers/phy/tegra/pcie-p2u-tegra194.c | 109 ++
include/uapi/linux/pci_regs.h | 22 +-
20 files changed, 2569 insertions(+), 43 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
create mode 100644 drivers/phy/tegra/pcie-p2u-tegra194.c
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
kthota@nvidia.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
linux-tegra@vger.kernel.org, vidyas@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V7 00/15] Add Tegra194 PCIe support
Date: Fri, 17 May 2019 18:08:31 +0530 [thread overview]
Message-ID: <20190517123846.3708-1-vidyas@nvidia.com> (raw)
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe
controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe
core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used
to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks)
to PCIe controller
This patch series
- Adds support for P2U PHY driver
- Adds support for PCIe host controller
- Adds device tree nodes each PCIe controllers
- Enables nodes applicable to p2972-0000 platform
- Adds helper APIs in Designware core driver to get capability regs offset
- Adds defines for new feature registers of PCIe spec revision 4
- Makes changes in DesignWare core driver to get Tegra194 PCIe working
Testing done on P2972-0000 platform
- Able to get PCIe link up with on-board Marvel eSATA controller
- Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot
- Able to do data transfers with both SATA drives and NVMe cards
Note
- Enabling x8 slot on P2972-0000 platform requires pinmux driver for Tegra194.
It is being worked on currently and hence Controller:5 (i.e. x8 slot) is
disabled in this patch series. A future patch series would enable this.
- This series is based on top of the following series
Jisheng's patches to add support to .remove() in Designware sub-system
https://patchwork.kernel.org/project/linux-pci/list/?series=98559
(Jisheng's patches are now accepted and applied for v5.2)
My patches made on top of Jisheng's patches to export various symbols
https://patchwork.kernel.org/project/linux-pci/list/?series=101259
Changes since [v6]:
* Took care of review comments from Rob
* Added a quirk to disable MSI for root ports
* Removed using pcie_pme_disable_msi() API in host controller driver
Changes since [v5]:
* Removed patch that exports pcie_bus_config symbol
* Took care of review comments from Thierry and Rob
Changes since [v4]:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
to pcie-designware.c file based on Bjorn's review comments
Changes since [v3]:
* Rebased on top of linux-next top of the tree
* Addressed Gustavo's comments and added his Ack for some of the changes.
Changes since [v2]:
* Addressed review comments from Thierry
Changes since [v1]:
* Addressed review comments from Bjorn, Thierry, Jonathan, Rob & Kishon
* Added more patches in v2 series
Vidya Sagar (15):
PCI: Add #defines for some of PCIe spec r4.0 features
PCI: Disable MSI for Tegra194 root port
PCI: dwc: Perform dbi regs write lock towards the end
PCI: dwc: Move config space capability search API
PCI: dwc: Add ext config space capability search API
dt-bindings: PCI: designware: Add binding for CDM register check
PCI: dwc: Add support to enable CDM register check
dt-bindings: Add PCIe supports-clkreq property
dt-bindings: PCI: tegra: Add device tree support for Tegra194
dt-bindings: PHY: P2U: Add Tegra194 P2U block
arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
arm64: tegra: Enable PCIe slots in P2972-0000 board
phy: tegra: Add PCIe PIPE2UPHY support
PCI: tegra: Add Tegra194 PCIe support
arm64: Add Tegra194 PCIe driver to defconfig
.../bindings/pci/designware-pcie.txt | 5 +
.../bindings/pci/nvidia,tegra194-pcie.txt | 158 ++
Documentation/devicetree/bindings/pci/pci.txt | 5 +
.../bindings/phy/phy-tegra194-p2u.txt | 28 +
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
.../boot/dts/nvidia/tegra194-p2972-0000.dts | 41 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 437 +++++
arch/arm64/configs/defconfig | 1 +
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
.../pci/controller/dwc/pcie-designware-ep.c | 37 +-
.../pci/controller/dwc/pcie-designware-host.c | 14 +-
drivers/pci/controller/dwc/pcie-designware.c | 88 +
drivers/pci/controller/dwc/pcie-designware.h | 12 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1620 +++++++++++++++++
drivers/pci/quirks.c | 14 +
drivers/phy/tegra/Kconfig | 7 +
drivers/phy/tegra/Makefile | 1 +
drivers/phy/tegra/pcie-p2u-tegra194.c | 109 ++
include/uapi/linux/pci_regs.h | 22 +-
20 files changed, 2569 insertions(+), 43 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
create mode 100644 drivers/phy/tegra/pcie-p2u-tegra194.c
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
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next reply other threads:[~2019-05-17 12:38 UTC|newest]
Thread overview: 131+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-17 12:38 Vidya Sagar [this message]
2019-05-17 12:38 ` [PATCH V7 00/15] Add Tegra194 PCIe support Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 01/15] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 02/15] PCI: Disable MSI for Tegra194 root port Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:27 ` Thierry Reding
2019-05-21 10:27 ` Thierry Reding
2019-05-21 16:47 ` Vidya Sagar
2019-05-21 16:47 ` Vidya Sagar
2019-05-21 16:47 ` Vidya Sagar
2019-05-21 19:34 ` Vidya Sagar
2019-05-21 19:34 ` Vidya Sagar
2019-05-21 19:34 ` Vidya Sagar
2019-05-21 19:36 ` Bjorn Helgaas
2019-05-21 19:36 ` Bjorn Helgaas
2019-05-21 19:36 ` Bjorn Helgaas
2019-05-22 8:07 ` Vidya Sagar
2019-05-22 8:07 ` Vidya Sagar
2019-05-22 8:07 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 03/15] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:29 ` Thierry Reding
2019-05-21 10:29 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 04/15] PCI: dwc: Move config space capability search API Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:29 ` Thierry Reding
2019-05-21 10:29 ` Thierry Reding
2019-05-21 21:17 ` Bjorn Helgaas
2019-05-21 21:17 ` Bjorn Helgaas
2019-05-22 8:56 ` Vidya Sagar
2019-05-22 8:56 ` Vidya Sagar
2019-05-22 8:56 ` Vidya Sagar
2019-05-22 14:02 ` Bjorn Helgaas
2019-05-22 14:02 ` Bjorn Helgaas
2019-05-24 14:46 ` Vidya Sagar
2019-05-24 14:46 ` Vidya Sagar
2019-05-24 14:46 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 05/15] PCI: dwc: Add ext " Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:36 ` Thierry Reding
2019-05-21 10:36 ` Thierry Reding
2019-05-21 17:14 ` Vidya Sagar
2019-05-21 17:14 ` Vidya Sagar
2019-05-21 17:14 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 06/15] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:37 ` Thierry Reding
2019-05-21 10:37 ` Thierry Reding
2019-05-24 20:23 ` Rob Herring
2019-05-24 20:23 ` Rob Herring
2019-05-24 20:23 ` Rob Herring
2019-05-17 12:38 ` [PATCH V7 07/15] PCI: dwc: Add support to enable " Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:38 ` Thierry Reding
2019-05-21 10:38 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 08/15] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:39 ` Thierry Reding
2019-05-21 10:39 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 09/15] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:51 ` Thierry Reding
2019-05-21 10:51 ` Thierry Reding
2019-05-21 18:00 ` Vidya Sagar
2019-05-21 18:00 ` Vidya Sagar
2019-05-21 18:00 ` Vidya Sagar
2019-05-24 20:26 ` Rob Herring
2019-05-24 20:26 ` Rob Herring
2019-05-17 12:38 ` [PATCH V7 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:52 ` Thierry Reding
2019-05-21 10:52 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 13:03 ` Ard Biesheuvel
2019-05-17 13:03 ` Ard Biesheuvel
2019-05-17 17:38 ` Vidya Sagar
2019-05-17 17:38 ` Vidya Sagar
2019-05-17 17:38 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 10:54 ` Thierry Reding
2019-05-21 10:54 ` Thierry Reding
2019-05-21 18:17 ` Vidya Sagar
2019-05-21 18:17 ` Vidya Sagar
2019-05-21 18:17 ` Vidya Sagar
2019-05-22 13:48 ` Thierry Reding
2019-05-22 13:48 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 13/15] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 11:00 ` Thierry Reding
2019-05-21 11:00 ` Thierry Reding
2019-05-21 19:37 ` Vidya Sagar
2019-05-21 19:37 ` Vidya Sagar
2019-05-21 19:37 ` Vidya Sagar
2019-05-21 11:00 ` Thierry Reding
2019-05-21 11:00 ` Thierry Reding
2019-05-22 8:59 ` Vidya Sagar
2019-05-22 8:59 ` Vidya Sagar
2019-05-22 8:59 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 14/15] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-21 11:41 ` Thierry Reding
2019-05-21 11:41 ` Thierry Reding
2019-05-22 12:05 ` Vidya Sagar
2019-05-22 12:05 ` Vidya Sagar
2019-05-22 12:05 ` Vidya Sagar
2019-05-22 14:14 ` Thierry Reding
2019-05-22 14:14 ` Thierry Reding
2019-05-24 18:07 ` Vidya Sagar
2019-05-24 18:07 ` Vidya Sagar
2019-05-24 18:07 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 15/15] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
2019-05-17 12:38 ` Vidya Sagar
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