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From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Dhinakaran Pandiyan" <dhinakaran.pandiyan@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"José Roberto de Souza" <jose.souza@intel.com>,
	stable@vger.kernel.org
Subject: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
Date: Wed, 17 Jul 2019 15:34:51 -0700	[thread overview]
Message-ID: <20190717223451.2595-1-dhinakaran.pandiyan@intel.com> (raw)

A single 32-bit PSR2 training pattern field follows the sixteen element
array of PSR table entries in the VBT spec. But, we incorrectly define
this PSR2 field for each of the PSR table entries. As a result, the PSR1
training pattern duration for any panel_type != 0 will be parsed
incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
version >= 226 will also be wrong.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: stable@vger.kernel.org
Cc: stable@vger.kernel.org #v5.2
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: François Guerraz <kubrick@fgv6.net>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 21501d565327..b416b394b641 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 93f5c9d204d6..09cd37fb0b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -481,13 +481,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
Date: Wed, 17 Jul 2019 15:34:51 -0700	[thread overview]
Message-ID: <20190717223451.2595-1-dhinakaran.pandiyan@intel.com> (raw)

A single 32-bit PSR2 training pattern field follows the sixteen element
array of PSR table entries in the VBT spec. But, we incorrectly define
this PSR2 field for each of the PSR table entries. As a result, the PSR1
training pattern duration for any panel_type != 0 will be parsed
incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
version >= 226 will also be wrong.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: stable@vger.kernel.org
Cc: stable@vger.kernel.org #v5.2
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: François Guerraz <kubrick@fgv6.net>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 21501d565327..b416b394b641 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 93f5c9d204d6..09cd37fb0b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -481,13 +481,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

             reply	other threads:[~2019-07-17 22:37 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-17 22:34 Dhinakaran Pandiyan [this message]
2019-07-17 22:34 ` [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Dhinakaran Pandiyan
2019-07-17 23:19 ` ✓ Fi.CI.BAT: success for drm/i915/vbt: Fix VBT parsing for the PSR section (rev3) Patchwork
2019-07-18 19:14 ` [Intel-gfx] [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Rodrigo Vivi
2019-07-19  0:45 ` Sasha Levin
2019-07-22 23:13   ` [PATCH stable v5.2] " Dhinakaran Pandiyan
2019-07-24 12:06     ` Greg KH
2019-07-24 17:27       ` Souza, Jose
2019-07-24 17:27         ` Souza, Jose
2019-07-24 17:40         ` [Intel-gfx] " Rodrigo Vivi
2019-07-24 17:40           ` Rodrigo Vivi
2019-07-30 15:19           ` [Intel-gfx] " Rodrigo Vivi
2019-07-30 15:19             ` Rodrigo Vivi
2019-07-30 15:27             ` [Intel-gfx] " Greg KH
2019-07-30 16:22               ` Rodrigo Vivi
2019-07-30 16:27                 ` Greg KH
2019-07-30 16:56                   ` Rodrigo Vivi
2019-07-30 16:56                     ` Rodrigo Vivi
2019-07-30 17:08                     ` Greg KH
2019-07-30 18:24                       ` Pandiyan, Dhinakaran
2019-07-30 20:42   ` [Intel-gfx] [PATCH] " Rodrigo Vivi
2019-07-30 21:48     ` Sasha Levin
2019-07-30 21:48       ` Sasha Levin
2019-07-31 17:14       ` [Intel-gfx] " Vivi, Rodrigo
2019-07-31 17:14         ` Vivi, Rodrigo
2019-07-31 19:23         ` [Intel-gfx] " Sasha Levin
2019-07-31 19:23           ` Sasha Levin
  -- strict thread matches above, loose matches on Subject: below --
2019-08-05  5:58 FAILED: patch "[PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section" failed to apply to 5.2-stable tree gregkh
2019-08-05 22:49 ` [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section José Roberto de Souza
2019-08-06  7:44   ` Jani Nikula
2019-08-07 19:37     ` Souza, Jose
2019-08-08  5:57       ` gregkh
2019-08-08  9:03     ` Greg KH
2019-07-16 22:03 Dhinakaran Pandiyan
2019-07-16 22:10 ` Pandiyan, Dhinakaran
2019-07-17 16:41   ` Souza, Jose
2019-07-17 16:56     ` Rodrigo Vivi
2019-07-17 11:35 ` Ville Syrjälä
2019-07-17 23:45   ` Pandiyan, Dhinakaran

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