From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, Chih-Min Chao <chihmin.chao@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [Qemu-devel] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Date: Wed, 18 Sep 2019 07:56:15 -0700 [thread overview]
Message-ID: <20190918145640.17349-24-palmer@sifive.com> (raw)
In-Reply-To: <20190918145640.17349-1-palmer@sifive.com>
From: Bin Meng <bmeng.cn@gmail.com>
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/Makefile.objs | 2 +-
hw/riscv/sifive_e.c | 4 +-
hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 79 ++++++++++-----------
include/hw/riscv/sifive_e_prci.h | 69 ++++++++++++++++++
include/hw/riscv/sifive_prci.h | 71 ------------------
5 files changed, 111 insertions(+), 114 deletions(-)
rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (51%)
create mode 100644 include/hw/riscv/sifive_e_prci.h
delete mode 100644 include/hw/riscv/sifive_prci.h
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index eb9d4f9ffc..c8596977a8 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -2,9 +2,9 @@ obj-y += boot.o
obj-$(CONFIG_SPIKE) += riscv_htif.o
obj-$(CONFIG_HART) += riscv_hart.o
obj-$(CONFIG_SIFIVE_E) += sifive_e.o
+obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o
obj-$(CONFIG_SIFIVE) += sifive_clint.o
obj-$(CONFIG_SIFIVE) += sifive_gpio.o
-obj-$(CONFIG_SIFIVE) += sifive_prci.o
obj-$(CONFIG_SIFIVE) += sifive_plic.o
obj-$(CONFIG_SIFIVE) += sifive_test.o
obj-$(CONFIG_SIFIVE_U) += sifive_u.o
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 792d75a1a3..1428a99fce 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -40,9 +40,9 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
-#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
+#include "hw/riscv/sifive_e_prci.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
@@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
- sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
+ sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
/* GPIO */
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_e_prci.c
similarity index 51%
rename from hw/riscv/sifive_prci.c
rename to hw/riscv/sifive_e_prci.c
index c413f0cb76..b6d32db935 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -1,5 +1,5 @@
/*
- * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt)
+ * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt)
*
* Copyright (c) 2017 SiFive, Inc.
*
@@ -23,19 +23,19 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
-#include "hw/riscv/sifive_prci.h"
+#include "hw/riscv/sifive_e_prci.h"
-static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
+static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
{
- SiFivePRCIState *s = opaque;
+ SiFiveEPRCIState *s = opaque;
switch (addr) {
- case SIFIVE_PRCI_HFROSCCFG:
+ case SIFIVE_E_PRCI_HFROSCCFG:
return s->hfrosccfg;
- case SIFIVE_PRCI_HFXOSCCFG:
+ case SIFIVE_E_PRCI_HFXOSCCFG:
return s->hfxosccfg;
- case SIFIVE_PRCI_PLLCFG:
+ case SIFIVE_E_PRCI_PLLCFG:
return s->pllcfg;
- case SIFIVE_PRCI_PLLOUTDIV:
+ case SIFIVE_E_PRCI_PLLOUTDIV:
return s->plloutdiv;
}
qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
@@ -43,27 +43,27 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
return 0;
}
-static void sifive_prci_write(void *opaque, hwaddr addr,
- uint64_t val64, unsigned int size)
+static void sifive_e_prci_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
{
- SiFivePRCIState *s = opaque;
+ SiFiveEPRCIState *s = opaque;
switch (addr) {
- case SIFIVE_PRCI_HFROSCCFG:
+ case SIFIVE_E_PRCI_HFROSCCFG:
s->hfrosccfg = (uint32_t) val64;
/* OSC stays ready */
- s->hfrosccfg |= SIFIVE_PRCI_HFROSCCFG_RDY;
+ s->hfrosccfg |= SIFIVE_E_PRCI_HFROSCCFG_RDY;
break;
- case SIFIVE_PRCI_HFXOSCCFG:
+ case SIFIVE_E_PRCI_HFXOSCCFG:
s->hfxosccfg = (uint32_t) val64;
/* OSC stays ready */
- s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY;
+ s->hfxosccfg |= SIFIVE_E_PRCI_HFXOSCCFG_RDY;
break;
- case SIFIVE_PRCI_PLLCFG:
+ case SIFIVE_E_PRCI_PLLCFG:
s->pllcfg = (uint32_t) val64;
/* PLL stays locked */
- s->pllcfg |= SIFIVE_PRCI_PLLCFG_LOCK;
+ s->pllcfg |= SIFIVE_E_PRCI_PLLCFG_LOCK;
break;
- case SIFIVE_PRCI_PLLOUTDIV:
+ case SIFIVE_E_PRCI_PLLOUTDIV:
s->plloutdiv = (uint32_t) val64;
break;
default:
@@ -72,9 +72,9 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
}
}
-static const MemoryRegionOps sifive_prci_ops = {
- .read = sifive_prci_read,
- .write = sifive_prci_write,
+static const MemoryRegionOps sifive_e_prci_ops = {
+ .read = sifive_e_prci_read,
+ .write = sifive_e_prci_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
@@ -82,43 +82,42 @@ static const MemoryRegionOps sifive_prci_ops = {
}
};
-static void sifive_prci_init(Object *obj)
+static void sifive_e_prci_init(Object *obj)
{
- SiFivePRCIState *s = SIFIVE_PRCI(obj);
+ SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj);
- memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s,
- TYPE_SIFIVE_PRCI, 0x8000);
+ memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s,
+ TYPE_SIFIVE_E_PRCI, 0x8000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
- s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
- s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
- s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
- SIFIVE_PRCI_PLLCFG_LOCK);
- s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
-
+ s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
+ s->hfxosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
+ s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS |
+ SIFIVE_E_PRCI_PLLCFG_LOCK);
+ s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1;
}
-static const TypeInfo sifive_prci_info = {
- .name = TYPE_SIFIVE_PRCI,
+static const TypeInfo sifive_e_prci_info = {
+ .name = TYPE_SIFIVE_E_PRCI,
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SiFivePRCIState),
- .instance_init = sifive_prci_init,
+ .instance_size = sizeof(SiFiveEPRCIState),
+ .instance_init = sifive_e_prci_init,
};
-static void sifive_prci_register_types(void)
+static void sifive_e_prci_register_types(void)
{
- type_register_static(&sifive_prci_info);
+ type_register_static(&sifive_e_prci_info);
}
-type_init(sifive_prci_register_types)
+type_init(sifive_e_prci_register_types)
/*
* Create PRCI device.
*/
-DeviceState *sifive_prci_create(hwaddr addr)
+DeviceState *sifive_e_prci_create(hwaddr addr)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI);
+ DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h
new file mode 100644
index 0000000000..c4b76aa17a
--- /dev/null
+++ b/include/hw/riscv/sifive_e_prci.h
@@ -0,0 +1,69 @@
+/*
+ * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SIFIVE_E_PRCI_H
+#define HW_SIFIVE_E_PRCI_H
+
+enum {
+ SIFIVE_E_PRCI_HFROSCCFG = 0x0,
+ SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
+ SIFIVE_E_PRCI_PLLCFG = 0x8,
+ SIFIVE_E_PRCI_PLLOUTDIV = 0xC
+};
+
+enum {
+ SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
+ SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30)
+};
+
+enum {
+ SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
+ SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30)
+};
+
+enum {
+ SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
+ SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
+ SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
+ SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31)
+};
+
+enum {
+ SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
+};
+
+#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
+
+#define SIFIVE_E_PRCI(obj) \
+ OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
+
+typedef struct SiFiveEPRCIState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion mmio;
+ uint32_t hfrosccfg;
+ uint32_t hfxosccfg;
+ uint32_t pllcfg;
+ uint32_t plloutdiv;
+} SiFiveEPRCIState;
+
+DeviceState *sifive_e_prci_create(hwaddr addr);
+
+#endif
diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h
deleted file mode 100644
index 8b7de134f8..0000000000
--- a/include/hw/riscv/sifive_prci.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_PRCI_H
-#define HW_SIFIVE_PRCI_H
-
-#include "hw/sysbus.h"
-
-enum {
- SIFIVE_PRCI_HFROSCCFG = 0x0,
- SIFIVE_PRCI_HFXOSCCFG = 0x4,
- SIFIVE_PRCI_PLLCFG = 0x8,
- SIFIVE_PRCI_PLLOUTDIV = 0xC
-};
-
-enum {
- SIFIVE_PRCI_HFROSCCFG_RDY = (1 << 31),
- SIFIVE_PRCI_HFROSCCFG_EN = (1 << 30)
-};
-
-enum {
- SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31),
- SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30)
-};
-
-enum {
- SIFIVE_PRCI_PLLCFG_PLLSEL = (1 << 16),
- SIFIVE_PRCI_PLLCFG_REFSEL = (1 << 17),
- SIFIVE_PRCI_PLLCFG_BYPASS = (1 << 18),
- SIFIVE_PRCI_PLLCFG_LOCK = (1 << 31)
-};
-
-enum {
- SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
-};
-
-#define TYPE_SIFIVE_PRCI "riscv.sifive.prci"
-
-#define SIFIVE_PRCI(obj) \
- OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI)
-
-typedef struct SiFivePRCIState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
- uint32_t hfrosccfg;
- uint32_t hfxosccfg;
- uint32_t pllcfg;
- uint32_t plloutdiv;
-} SiFivePRCIState;
-
-DeviceState *sifive_prci_create(hwaddr addr);
-
-#endif
--
2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Bin Meng <bmeng.cn@gmail.com>,
Chih-Min Chao <chihmin.chao@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-riscv] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Date: Wed, 18 Sep 2019 07:56:15 -0700 [thread overview]
Message-ID: <20190918145640.17349-24-palmer@sifive.com> (raw)
In-Reply-To: <20190918145640.17349-1-palmer@sifive.com>
From: Bin Meng <bmeng.cn@gmail.com>
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/Makefile.objs | 2 +-
hw/riscv/sifive_e.c | 4 +-
hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 79 ++++++++++-----------
include/hw/riscv/sifive_e_prci.h | 69 ++++++++++++++++++
include/hw/riscv/sifive_prci.h | 71 ------------------
5 files changed, 111 insertions(+), 114 deletions(-)
rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (51%)
create mode 100644 include/hw/riscv/sifive_e_prci.h
delete mode 100644 include/hw/riscv/sifive_prci.h
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index eb9d4f9ffc..c8596977a8 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -2,9 +2,9 @@ obj-y += boot.o
obj-$(CONFIG_SPIKE) += riscv_htif.o
obj-$(CONFIG_HART) += riscv_hart.o
obj-$(CONFIG_SIFIVE_E) += sifive_e.o
+obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o
obj-$(CONFIG_SIFIVE) += sifive_clint.o
obj-$(CONFIG_SIFIVE) += sifive_gpio.o
-obj-$(CONFIG_SIFIVE) += sifive_prci.o
obj-$(CONFIG_SIFIVE) += sifive_plic.o
obj-$(CONFIG_SIFIVE) += sifive_test.o
obj-$(CONFIG_SIFIVE_U) += sifive_u.o
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 792d75a1a3..1428a99fce 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -40,9 +40,9 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
-#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
+#include "hw/riscv/sifive_e_prci.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
@@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
- sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
+ sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
/* GPIO */
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_e_prci.c
similarity index 51%
rename from hw/riscv/sifive_prci.c
rename to hw/riscv/sifive_e_prci.c
index c413f0cb76..b6d32db935 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -1,5 +1,5 @@
/*
- * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt)
+ * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt)
*
* Copyright (c) 2017 SiFive, Inc.
*
@@ -23,19 +23,19 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
-#include "hw/riscv/sifive_prci.h"
+#include "hw/riscv/sifive_e_prci.h"
-static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
+static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
{
- SiFivePRCIState *s = opaque;
+ SiFiveEPRCIState *s = opaque;
switch (addr) {
- case SIFIVE_PRCI_HFROSCCFG:
+ case SIFIVE_E_PRCI_HFROSCCFG:
return s->hfrosccfg;
- case SIFIVE_PRCI_HFXOSCCFG:
+ case SIFIVE_E_PRCI_HFXOSCCFG:
return s->hfxosccfg;
- case SIFIVE_PRCI_PLLCFG:
+ case SIFIVE_E_PRCI_PLLCFG:
return s->pllcfg;
- case SIFIVE_PRCI_PLLOUTDIV:
+ case SIFIVE_E_PRCI_PLLOUTDIV:
return s->plloutdiv;
}
qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
@@ -43,27 +43,27 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
return 0;
}
-static void sifive_prci_write(void *opaque, hwaddr addr,
- uint64_t val64, unsigned int size)
+static void sifive_e_prci_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
{
- SiFivePRCIState *s = opaque;
+ SiFiveEPRCIState *s = opaque;
switch (addr) {
- case SIFIVE_PRCI_HFROSCCFG:
+ case SIFIVE_E_PRCI_HFROSCCFG:
s->hfrosccfg = (uint32_t) val64;
/* OSC stays ready */
- s->hfrosccfg |= SIFIVE_PRCI_HFROSCCFG_RDY;
+ s->hfrosccfg |= SIFIVE_E_PRCI_HFROSCCFG_RDY;
break;
- case SIFIVE_PRCI_HFXOSCCFG:
+ case SIFIVE_E_PRCI_HFXOSCCFG:
s->hfxosccfg = (uint32_t) val64;
/* OSC stays ready */
- s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY;
+ s->hfxosccfg |= SIFIVE_E_PRCI_HFXOSCCFG_RDY;
break;
- case SIFIVE_PRCI_PLLCFG:
+ case SIFIVE_E_PRCI_PLLCFG:
s->pllcfg = (uint32_t) val64;
/* PLL stays locked */
- s->pllcfg |= SIFIVE_PRCI_PLLCFG_LOCK;
+ s->pllcfg |= SIFIVE_E_PRCI_PLLCFG_LOCK;
break;
- case SIFIVE_PRCI_PLLOUTDIV:
+ case SIFIVE_E_PRCI_PLLOUTDIV:
s->plloutdiv = (uint32_t) val64;
break;
default:
@@ -72,9 +72,9 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
}
}
-static const MemoryRegionOps sifive_prci_ops = {
- .read = sifive_prci_read,
- .write = sifive_prci_write,
+static const MemoryRegionOps sifive_e_prci_ops = {
+ .read = sifive_e_prci_read,
+ .write = sifive_e_prci_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
@@ -82,43 +82,42 @@ static const MemoryRegionOps sifive_prci_ops = {
}
};
-static void sifive_prci_init(Object *obj)
+static void sifive_e_prci_init(Object *obj)
{
- SiFivePRCIState *s = SIFIVE_PRCI(obj);
+ SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj);
- memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s,
- TYPE_SIFIVE_PRCI, 0x8000);
+ memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s,
+ TYPE_SIFIVE_E_PRCI, 0x8000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
- s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
- s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
- s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
- SIFIVE_PRCI_PLLCFG_LOCK);
- s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
-
+ s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
+ s->hfxosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
+ s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS |
+ SIFIVE_E_PRCI_PLLCFG_LOCK);
+ s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1;
}
-static const TypeInfo sifive_prci_info = {
- .name = TYPE_SIFIVE_PRCI,
+static const TypeInfo sifive_e_prci_info = {
+ .name = TYPE_SIFIVE_E_PRCI,
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SiFivePRCIState),
- .instance_init = sifive_prci_init,
+ .instance_size = sizeof(SiFiveEPRCIState),
+ .instance_init = sifive_e_prci_init,
};
-static void sifive_prci_register_types(void)
+static void sifive_e_prci_register_types(void)
{
- type_register_static(&sifive_prci_info);
+ type_register_static(&sifive_e_prci_info);
}
-type_init(sifive_prci_register_types)
+type_init(sifive_e_prci_register_types)
/*
* Create PRCI device.
*/
-DeviceState *sifive_prci_create(hwaddr addr)
+DeviceState *sifive_e_prci_create(hwaddr addr)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI);
+ DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h
new file mode 100644
index 0000000000..c4b76aa17a
--- /dev/null
+++ b/include/hw/riscv/sifive_e_prci.h
@@ -0,0 +1,69 @@
+/*
+ * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SIFIVE_E_PRCI_H
+#define HW_SIFIVE_E_PRCI_H
+
+enum {
+ SIFIVE_E_PRCI_HFROSCCFG = 0x0,
+ SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
+ SIFIVE_E_PRCI_PLLCFG = 0x8,
+ SIFIVE_E_PRCI_PLLOUTDIV = 0xC
+};
+
+enum {
+ SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
+ SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30)
+};
+
+enum {
+ SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
+ SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30)
+};
+
+enum {
+ SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
+ SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
+ SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
+ SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31)
+};
+
+enum {
+ SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
+};
+
+#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
+
+#define SIFIVE_E_PRCI(obj) \
+ OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
+
+typedef struct SiFiveEPRCIState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion mmio;
+ uint32_t hfrosccfg;
+ uint32_t hfxosccfg;
+ uint32_t pllcfg;
+ uint32_t plloutdiv;
+} SiFiveEPRCIState;
+
+DeviceState *sifive_e_prci_create(hwaddr addr);
+
+#endif
diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h
deleted file mode 100644
index 8b7de134f8..0000000000
--- a/include/hw/riscv/sifive_prci.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_PRCI_H
-#define HW_SIFIVE_PRCI_H
-
-#include "hw/sysbus.h"
-
-enum {
- SIFIVE_PRCI_HFROSCCFG = 0x0,
- SIFIVE_PRCI_HFXOSCCFG = 0x4,
- SIFIVE_PRCI_PLLCFG = 0x8,
- SIFIVE_PRCI_PLLOUTDIV = 0xC
-};
-
-enum {
- SIFIVE_PRCI_HFROSCCFG_RDY = (1 << 31),
- SIFIVE_PRCI_HFROSCCFG_EN = (1 << 30)
-};
-
-enum {
- SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31),
- SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30)
-};
-
-enum {
- SIFIVE_PRCI_PLLCFG_PLLSEL = (1 << 16),
- SIFIVE_PRCI_PLLCFG_REFSEL = (1 << 17),
- SIFIVE_PRCI_PLLCFG_BYPASS = (1 << 18),
- SIFIVE_PRCI_PLLCFG_LOCK = (1 << 31)
-};
-
-enum {
- SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
-};
-
-#define TYPE_SIFIVE_PRCI "riscv.sifive.prci"
-
-#define SIFIVE_PRCI(obj) \
- OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI)
-
-typedef struct SiFivePRCIState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
- uint32_t hfrosccfg;
- uint32_t hfxosccfg;
- uint32_t pllcfg;
- uint32_t plloutdiv;
-} SiFivePRCIState;
-
-DeviceState *sifive_prci_create(hwaddr addr);
-
-#endif
--
2.21.0
next prev parent reply other threads:[~2019-09-18 15:57 UTC|newest]
Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-18 14:55 [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 01/48] riscv: sifive_u: Add support for loading initrd Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 03/48] riscv: sifive_u: Fix clock-names property for ethernet node Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 06/48] riscv: plic: Remove unused interrupt functions Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 07/48] target/riscv: Create function to test if FP is enabled Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4 Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 10/48] riscv: Add a helper routine for finding firmware Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 11/48] riscv: Resolve full path of the given bios image Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-24 10:17 ` Peter Maydell
2019-09-24 10:17 ` Peter Maydell
2019-10-02 21:38 ` Alistair Francis
2019-10-02 21:38 ` Alistair Francis
2019-09-18 14:56 ` [Qemu-devel] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 13/48] riscv: sifive_test: Add reset functionality Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 18/48] riscv: hw: Change create_fdt() to return void Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 21/48] riscv: roms: Remove executable attribute of opensbi images Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 22/48] riscv: sifive_u: Remove the unnecessary include of prci header Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` Palmer Dabbelt [this message]
2019-09-18 14:56 ` [Qemu-riscv] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate() Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2 Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540 Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 42/48] riscv: sifive_u: Fix broken GEM support Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 45/48] target/riscv: Use both register name and ABI name Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 46/48] target/riscv: Fix mstatus dirty mask Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 48/48] gdbstub: riscv: fix the fflags registers Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-19 12:26 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 Peter Maydell
2019-09-19 12:26 ` [Qemu-riscv] " Peter Maydell
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