From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: narmstrong@baylibre.com, jbrunet@baylibre.com,
robh+dt@kernel.org, mark.rutland@arm.com,
linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
khilman@baylibre.com
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH 5/6] ARM: dts: meson8: add the DDR clock controller
Date: Sat, 21 Sep 2019 17:18:34 +0200 [thread overview]
Message-ID: <20190921151835.770263-6-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com>
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 4f59a4c8f036..257c1364864c 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -3,6 +3,7 @@
* Copyright 2014 Carlo Caione <carlo@caione.org>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
@@ -195,6 +196,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -455,8 +464,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
- clocks = <&xtal>;
- clock-names = "xtal";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: narmstrong@baylibre.com, jbrunet@baylibre.com,
robh+dt@kernel.org, mark.rutland@arm.com,
linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
khilman@baylibre.com
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: [PATCH 5/6] ARM: dts: meson8: add the DDR clock controller
Date: Sat, 21 Sep 2019 17:18:34 +0200 [thread overview]
Message-ID: <20190921151835.770263-6-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com>
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 4f59a4c8f036..257c1364864c 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -3,6 +3,7 @@
* Copyright 2014 Carlo Caione <carlo@caione.org>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
@@ -195,6 +196,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -455,8 +464,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
- clocks = <&xtal>;
- clock-names = "xtal";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.23.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: narmstrong@baylibre.com, jbrunet@baylibre.com,
robh+dt@kernel.org, mark.rutland@arm.com,
linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
khilman@baylibre.com
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: [PATCH 5/6] ARM: dts: meson8: add the DDR clock controller
Date: Sat, 21 Sep 2019 17:18:34 +0200 [thread overview]
Message-ID: <20190921151835.770263-6-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com>
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 4f59a4c8f036..257c1364864c 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -3,6 +3,7 @@
* Copyright 2014 Carlo Caione <carlo@caione.org>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
@@ -195,6 +196,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -455,8 +464,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
- clocks = <&xtal>;
- clock-names = "xtal";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.23.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2019-09-21 15:19 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-21 15:18 [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 1/6] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-10-02 14:19 ` Rob Herring
2019-10-02 14:19 ` Rob Herring
2019-10-02 14:19 ` Rob Herring
2019-09-21 15:18 ` [PATCH 2/6] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-10-01 13:29 ` Jerome Brunet
2019-10-01 13:29 ` Jerome Brunet
2019-10-01 13:29 ` Jerome Brunet
2019-10-01 18:53 ` Martin Blumenstingl
2019-10-01 18:53 ` Martin Blumenstingl
2019-10-01 18:53 ` Martin Blumenstingl
2019-10-01 18:53 ` Martin Blumenstingl
2019-10-02 9:04 ` Jerome Brunet
2019-10-02 9:04 ` Jerome Brunet
2019-10-02 9:04 ` Jerome Brunet
2019-09-21 15:18 ` [PATCH 3/6] clk: meson: meson8b: use of_clk_hw_register to register the clocks Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 4/6] clk: meson: meson8b: add the ddr_pll input for the audio clocks Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl [this message]
2019-09-21 15:18 ` [PATCH 5/6] ARM: dts: meson8: add the DDR clock controller Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 6/6] ARM: dts: meson8b: " Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-23 10:06 ` [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b Jerome Brunet
2019-09-23 10:06 ` Jerome Brunet
2019-09-23 10:06 ` Jerome Brunet
2019-09-23 10:06 ` Jerome Brunet
2019-09-23 20:49 ` Martin Blumenstingl
2019-09-23 20:49 ` Martin Blumenstingl
2019-09-23 20:49 ` Martin Blumenstingl
2019-10-01 13:33 ` Jerome Brunet
2019-10-01 13:33 ` Jerome Brunet
2019-10-01 13:33 ` Jerome Brunet
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