All of lore.kernel.org
 help / color / mirror / Atom feed
From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Damien Le Moal <Damien.LeMoal@wdc.com>,
	Atish Patra <atish.patra@wdc.com>
Subject: [PATCH 10/15] riscv: read the hart ID from mhartid on boot
Date: Thu, 17 Oct 2019 19:37:38 +0200	[thread overview]
Message-ID: <20191017173743.5430-11-hch@lst.de> (raw)
In-Reply-To: <20191017173743.5430-1-hch@lst.de>

From: Damien Le Moal <Damien.LeMoal@wdc.com>

When in M-Mode, we can use the mhartid CSR to get the ID of the running
HART. Doing so, direct M-Mode boot without firmware is possible.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/include/asm/csr.h | 1 +
 arch/riscv/kernel/head.S     | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 0dae5c361f29..d0b5113e1a54 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -81,6 +81,7 @@
 #define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
 
 /* symbolic CSR names: */
+#define CSR_MHARTID		0xf14
 #define CSR_MSTATUS		0x300
 #define CSR_MIE			0x304
 #define CSR_MTVEC		0x305
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 679e63d29edb..583784cb3a32 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -50,6 +50,14 @@ _start_kernel:
 	csrw CSR_XIE, zero
 	csrw CSR_XIP, zero
 
+#ifdef CONFIG_RISCV_M_MODE
+	/*
+	 * The hartid in a0 is expected later on, and we have no firmware
+	 * to hand it to us.
+	 */
+	csrr a0, CSR_MHARTID
+#endif
+
 	/* Load the global pointer */
 .option push
 .option norelax
-- 
2.20.1


WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Cc: Atish Patra <atish.patra@wdc.com>,
	Damien Le Moal <Damien.LeMoal@wdc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 10/15] riscv: read the hart ID from mhartid on boot
Date: Thu, 17 Oct 2019 19:37:38 +0200	[thread overview]
Message-ID: <20191017173743.5430-11-hch@lst.de> (raw)
In-Reply-To: <20191017173743.5430-1-hch@lst.de>

From: Damien Le Moal <Damien.LeMoal@wdc.com>

When in M-Mode, we can use the mhartid CSR to get the ID of the running
HART. Doing so, direct M-Mode boot without firmware is possible.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/include/asm/csr.h | 1 +
 arch/riscv/kernel/head.S     | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 0dae5c361f29..d0b5113e1a54 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -81,6 +81,7 @@
 #define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
 
 /* symbolic CSR names: */
+#define CSR_MHARTID		0xf14
 #define CSR_MSTATUS		0x300
 #define CSR_MIE			0x304
 #define CSR_MTVEC		0x305
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 679e63d29edb..583784cb3a32 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -50,6 +50,14 @@ _start_kernel:
 	csrw CSR_XIE, zero
 	csrw CSR_XIP, zero
 
+#ifdef CONFIG_RISCV_M_MODE
+	/*
+	 * The hartid in a0 is expected later on, and we have no firmware
+	 * to hand it to us.
+	 */
+	csrr a0, CSR_MHARTID
+#endif
+
 	/* Load the global pointer */
 .option push
 .option norelax
-- 
2.20.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2019-10-17 17:38 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-17 17:37 RISC-V nommu support v5 Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-17 17:37 ` [PATCH 01/15] riscv: cleanup <asm/bug.h> Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  2:50   ` Anup Patel
2019-10-18  2:50     ` Anup Patel
2019-10-23 22:04   ` Paul Walmsley
2019-10-23 22:04     ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 02/15] riscv: cleanup do_trap_break Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  2:51   ` Anup Patel
2019-10-18  2:51     ` Anup Patel
2019-10-23 22:05   ` Paul Walmsley
2019-10-23 22:05     ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 03/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  2:51   ` Anup Patel
2019-10-18  2:51     ` Anup Patel
2019-10-18 23:55   ` Paul Walmsley
2019-10-18 23:55     ` Paul Walmsley
2019-10-28  8:12     ` Christoph Hellwig
2019-10-28  8:12       ` Christoph Hellwig
2019-10-17 17:37 ` [PATCH 04/15] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  2:52   ` Anup Patel
2019-10-18  2:52     ` Anup Patel
2019-10-17 17:37 ` [PATCH 05/15] riscv: poison SBI calls " Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  2:53   ` Anup Patel
2019-10-18  2:53     ` Anup Patel
2019-10-17 17:37 ` [PATCH 06/15] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  2:53   ` Anup Patel
2019-10-18  2:53     ` Anup Patel
2019-10-17 17:37 ` [PATCH 07/15] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  2:55   ` Anup Patel
2019-10-18  2:55     ` Anup Patel
2019-10-17 17:37 ` [PATCH 08/15] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  2:57   ` Anup Patel
2019-10-18  2:57     ` Anup Patel
2019-10-17 17:37 ` [PATCH 09/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  3:00   ` Anup Patel
2019-10-18  3:00     ` Anup Patel
2019-11-14  7:39   ` Paul Walmsley
2019-11-14  7:39     ` Paul Walmsley
2019-10-17 17:37 ` Christoph Hellwig [this message]
2019-10-17 17:37   ` [PATCH 10/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-18  3:01   ` Anup Patel
2019-10-18  3:01     ` Anup Patel
2019-11-14  7:40   ` Paul Walmsley
2019-11-14  7:40     ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 11/15] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  3:01   ` Anup Patel
2019-10-18  3:01     ` Anup Patel
2019-10-17 17:37 ` [PATCH 12/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  3:05   ` Anup Patel
2019-10-18  3:05     ` Anup Patel
2019-10-17 17:37 ` [PATCH 13/15] riscv: add nommu support Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  3:04   ` Anup Patel
2019-10-18  3:04     ` Anup Patel
2019-10-17 17:37 ` [PATCH 14/15] riscv: provide a flat image loader Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  3:06   ` Anup Patel
2019-10-18  3:06     ` Anup Patel
2019-10-17 17:37 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-17 17:37   ` Christoph Hellwig
2019-10-18  3:06   ` Anup Patel
2019-10-18  3:06     ` Anup Patel
2019-10-18  3:08 ` RISC-V nommu support v5 Anup Patel
2019-10-18  3:08   ` Anup Patel
2019-10-18  3:29   ` Paul Walmsley
2019-10-18  3:29     ` Paul Walmsley
2019-10-18 15:25     ` Christoph Hellwig
2019-10-18 15:25       ` Christoph Hellwig
2019-10-18 23:46       ` Paul Walmsley
2019-10-18 23:46         ` Paul Walmsley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191017173743.5430-11-hch@lst.de \
    --to=hch@lst.de \
    --cc=atish.patra@wdc.com \
    --cc=damien.lemoal@wdc.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@sifive.com \
    --cc=paul.walmsley@sifive.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.