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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 31/34] hw/arm/acpi: simplify AML bit and/or statement
Date: Mon, 16 Dec 2019 11:09:01 +0000	[thread overview]
Message-ID: <20191216110904.30815-32-peter.maydell@linaro.org> (raw)
In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org>

From: Heyi Guo <guoheyi@huawei.com>

The last argument of AML bit and/or statement is the target variable,
so we don't need to use a NULL target and then an additional store
operation; using just aml_and() or aml_or() statement is enough.

Also update tests/data/acpi/virt/DSDT* to pass "make check".

Cc: Shannon Zhao <shannon.zhaosl@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Message-id: 20191209063719.23086-2-guoheyi@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c          |  16 ++++++++--------
 tests/data/acpi/virt/DSDT         | Bin 18470 -> 18462 bytes
 tests/data/acpi/virt/DSDT.memhp   | Bin 19807 -> 19799 bytes
 tests/data/acpi/virt/DSDT.numamem | Bin 18470 -> 18462 bytes
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 4cd50175e04..51b293e0a1e 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -267,17 +267,17 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
-    aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
-                                aml_name("CTRL")));
+    aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1D),
+                              aml_name("CTRL")));
 
     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
-    aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
-                                 aml_name("CDW1")));
+    aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
+                              aml_name("CDW1")));
     aml_append(ifctx, ifctx1);
 
     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
-    aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
-                                 aml_name("CDW1")));
+    aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
+                              aml_name("CDW1")));
     aml_append(ifctx, ifctx1);
 
     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
@@ -285,8 +285,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
     aml_append(method, ifctx);
 
     elsectx = aml_else();
-    aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
-                                  aml_name("CDW1")));
+    aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
+                               aml_name("CDW1")));
     aml_append(elsectx, aml_return(aml_arg(3)));
     aml_append(method, elsectx);
     aml_append(dev, method);
diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT
index bce76e3d23e99e6c5ef64c94c770282dd30ecdd0..05bcfc8a912f58f266aa906563ea01c24906717e 100644
GIT binary patch
delta 133
zcmZ2BfpOjhMlP3Nmk>D*1_q|2iCof5o%I{lJ2{y;?{412x!p#<jWgaq*qNm(o59&7
z+;D-%<VrV7_iE>mARjJS5V=5L(&S9WT970c2Uv;Nq{%?q7$gZ1761tsfcPNsCD{x4
MAmS{W8QoPG0j8@bzW@LL

delta 141
zcmbO?fpOUcMlP3Nmk>1%1_q`n6S<_B8XGpMcXBc{-rKy1bGwazA7{LOuro_nHiNTE
zxZwi7$(3%F{sq;}AwfP|vJ4<<fzYJMnT!RsAbBnhh%$*ulYv}gkTg_604z}e5&_99
R$zCV`m0@An{L@X95dZ+BD!u>!

diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
index b4b153fcdc30d211237fced6be1e99d3500bd276..c041a910fdf272cb89263bb636239ae3a5e1708d 100644
GIT binary patch
delta 132
zcmcaVi}Cs_MlP3NmymE@1_ma@iCof*O&is^IGH-{Zr;SX-A2HTGu}VgnWZb6!PzC;
zaDm6<N;gaQYUhw3A1+xCxj<mj<V?m|kR%reSc%xA$w1l|Bnc4~00|d>_#p8m*$ep~
L;w+mP-Q(B*s{AMU

delta 140
zcmcaUi}C&}MlP3Nmymd01_maViCof*T^rT9IGGynZQjJW-A2HVGu}VgnWZb6!PzC;
zaDm_CN;gaYf@<fGARjJS1`xGCXwu|N#)4XqJQoK<nZ%^YK&~-J8Y&?GmM8#;fMk|r
QFBE{vurO@?=@!QZ00dYn_y7O^

diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem
index bce76e3d23e99e6c5ef64c94c770282dd30ecdd0..05bcfc8a912f58f266aa906563ea01c24906717e 100644
GIT binary patch
delta 133
zcmZ2BfpOjhMlP3Nmk>D*1_q|2iCof5o%I{lJ2{y;?{412x!p#<jWgaq*qNm(o59&7
z+;D-%<VrV7_iE>mARjJS5V=5L(&S9WT970c2Uv;Nq{%?q7$gZ1761tsfcPNsCD{x4
MAmS{W8QoPG0j8@bzW@LL

delta 141
zcmbO?fpOUcMlP3Nmk>1%1_q`n6S<_B8XGpMcXBc{-rKy1bGwazA7{LOuro_nHiNTE
zxZwi7$(3%F{sq;}AwfP|vJ4<<fzYJMnT!RsAbBnhh%$*ulYv}gkTg_604z}e5&_99
R$zCV`m0@An{L@X95dZ+BD!u>!

-- 
2.20.1



  parent reply	other threads:[~2019-12-16 11:43 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-16 11:08 [PULL 00/34] target-arm queue Peter Maydell
2019-12-16 11:08 ` [PULL 01/34] target/arm: Add support for cortex-m7 CPU Peter Maydell
2019-12-16 11:08 ` [PULL 02/34] exynos4210_gic: Suppress gcc9 format-truncation warnings Peter Maydell
2019-12-16 11:08 ` [PULL 03/34] aspeed/i2c: Add support for pool buffer transfers Peter Maydell
2019-12-16 11:08 ` [PULL 04/34] aspeed/i2c: Check SRAM enablement on AST2500 Peter Maydell
2019-12-16 11:08 ` [PULL 05/34] aspeed: Add a DRAM memory region at the SoC level Peter Maydell
2019-12-16 11:08 ` [PULL 06/34] aspeed/i2c: Add support for DMA transfers Peter Maydell
2019-12-16 11:08 ` [PULL 07/34] aspeed/i2c: Add trace events Peter Maydell
2019-12-16 11:08 ` [PULL 08/34] aspeed/sdmc: Make ast2600 default 1G Peter Maydell
2019-12-16 11:08 ` [PULL 09/34] aspeed/scu: Fix W1C behavior Peter Maydell
2019-12-16 11:08 ` [PULL 10/34] watchdog/aspeed: Improve watchdog timeout message Peter Maydell
2019-12-16 11:08 ` [PULL 11/34] watchdog/aspeed: Fix AST2600 frequency behaviour Peter Maydell
2019-12-16 11:08 ` [PULL 12/34] aspeed/smc: Restore default AHB window mapping at reset Peter Maydell
2019-12-16 11:08 ` [PULL 13/34] aspeed/smc: Do not map disabled segment on the AST2600 Peter Maydell
2019-12-16 11:08 ` [PULL 14/34] aspeed/smc: Add AST2600 timings registers Peter Maydell
2019-12-16 11:08 ` [PULL 15/34] aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass Peter Maydell
2019-12-16 11:08 ` [PULL 16/34] aspeed: Add support for the tacoma-bmc board Peter Maydell
2019-12-16 11:08 ` [PULL 17/34] gpio: fix memory leak in aspeed_gpio_init() Peter Maydell
2019-12-16 11:08 ` [PULL 18/34] aspeed: Change the "scu" property definition Peter Maydell
2019-12-16 11:08 ` [PULL 19/34] aspeed: Change the "nic" " Peter Maydell
2019-12-16 11:08 ` [PULL 20/34] target/arm: Honor HCR_EL2.TID2 trapping requirements Peter Maydell
2019-12-16 11:08 ` [PULL 21/34] target/arm: Honor HCR_EL2.TID1 " Peter Maydell
2019-12-16 11:08 ` [PULL 22/34] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Peter Maydell
2019-12-16 11:08 ` [PULL 23/34] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 Peter Maydell
2019-12-16 11:08 ` [PULL 24/34] target/arm: Add support for missing Jazelle system registers Peter Maydell
2019-12-16 11:08 ` [PULL 25/34] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() Peter Maydell
2019-12-16 11:08 ` [PULL 26/34] tcg: cputlb: Add probe_read Peter Maydell
2019-12-16 11:08 ` [PULL 27/34] Memory: Enable writeback for given memory region Peter Maydell
2019-12-16 11:08 ` [PULL 28/34] migration: ram: Switch to ram block writeback Peter Maydell
2019-12-16 11:08 ` [PULL 29/34] target/arm: Add support for DC CVAP & DC CVADP ins Peter Maydell
2019-12-16 11:09 ` [PULL 30/34] hw/arm/sbsa-ref: Simplify by moving the gic in the machine state Peter Maydell
2019-12-16 11:09 ` Peter Maydell [this message]
2019-12-16 11:09 ` [PULL 32/34] hw/arm/acpi: enable SHPC native hot plug Peter Maydell
2019-12-16 11:09 ` [PULL 33/34] hw/arm/virt: Simplify by moving the gic in the machine state Peter Maydell
2019-12-16 11:09 ` [PULL 34/34] target/arm: ensure we use current exception state after SCR update Peter Maydell
2019-12-16 14:07 ` [PULL 00/34] target-arm queue Peter Maydell

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