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From: Pascal Paillet <p.paillet@st.com>
To: <rui.zhang@intel.com>, <edubezval@gmail.com>,
	<daniel.lezcano@linaro.org>, <amit.kucheria@verdurent.com>,
	<mcoquelin.stm32@gmail.com>, <alexandre.torgue@st.com>,
	<p.paillet@st.com>, <david.hernandezsanchez@st.com>,
	<horms+renesas@verge.net.au>, <wsa+renesas@sang-engineering.com>,
	<linux-pm@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH_V3 1/6] thermal: stm32: fix icifr register name
Date: Fri, 10 Jan 2020 11:16:00 +0100	[thread overview]
Message-ID: <20200110101605.24984-2-p.paillet@st.com> (raw)
In-Reply-To: <20200110101605.24984-1-p.paillet@st.com>

Fix a mistake with the ICIFR register name.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
---
 drivers/thermal/st/stm_thermal.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/thermal/st/stm_thermal.c b/drivers/thermal/st/stm_thermal.c
index cf9ddc52f30e..7835e109692e 100644
--- a/drivers/thermal/st/stm_thermal.c
+++ b/drivers/thermal/st/stm_thermal.c
@@ -30,7 +30,7 @@
 #define DTS_DR_OFFSET		0x1C
 #define DTS_SR_OFFSET		0x20
 #define DTS_ITENR_OFFSET	0x24
-#define DTS_CIFR_OFFSET		0x28
+#define DTS_ICIFR_OFFSET	0x28
 
 /* DTS_CFGR1 register mask definitions */
 #define HSREF_CLK_DIV_MASK	GENMASK(30, 24)
@@ -122,10 +122,10 @@ static irqreturn_t stm_thermal_alarm_irq_thread(int irq, void *sdata)
 	value = readl_relaxed(sensor->base + DTS_SR_OFFSET);
 
 	if ((value & LOW_THRESHOLD) == LOW_THRESHOLD)
-		writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+		writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
 
 	if ((value & HIGH_THRESHOLD) == HIGH_THRESHOLD)
-		writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+		writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
 
 	thermal_zone_device_update(sensor->th_dev, THERMAL_EVENT_UNSPECIFIED);
 
@@ -347,7 +347,7 @@ static int stm_enable_irq(struct stm_thermal_sensor *sensor)
 	 */
 
 	/* Make sure LOW_THRESHOLD IT is clear before enabling */
-	writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+	writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
 
 	/* Enable IT generation for low threshold */
 	value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
@@ -356,7 +356,7 @@ static int stm_enable_irq(struct stm_thermal_sensor *sensor)
 	/* Enable the low temperature threshold if needed */
 	if (sensor->low_temp_enabled) {
 		/* Make sure HIGH_THRESHOLD IT is clear before enabling */
-		writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+		writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
 
 		/* Enable IT generation for high threshold */
 		value |= HIGH_THRESHOLD;
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Pascal Paillet <p.paillet@st.com>
To: <rui.zhang@intel.com>, <edubezval@gmail.com>,
	<daniel.lezcano@linaro.org>,  <amit.kucheria@verdurent.com>,
	<mcoquelin.stm32@gmail.com>, <alexandre.torgue@st.com>,
	<p.paillet@st.com>, <david.hernandezsanchez@st.com>,
	<horms+renesas@verge.net.au>, <wsa+renesas@sang-engineering.com>,
	<linux-pm@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH_V3 1/6] thermal: stm32: fix icifr register name
Date: Fri, 10 Jan 2020 11:16:00 +0100	[thread overview]
Message-ID: <20200110101605.24984-2-p.paillet@st.com> (raw)
In-Reply-To: <20200110101605.24984-1-p.paillet@st.com>

Fix a mistake with the ICIFR register name.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
---
 drivers/thermal/st/stm_thermal.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/thermal/st/stm_thermal.c b/drivers/thermal/st/stm_thermal.c
index cf9ddc52f30e..7835e109692e 100644
--- a/drivers/thermal/st/stm_thermal.c
+++ b/drivers/thermal/st/stm_thermal.c
@@ -30,7 +30,7 @@
 #define DTS_DR_OFFSET		0x1C
 #define DTS_SR_OFFSET		0x20
 #define DTS_ITENR_OFFSET	0x24
-#define DTS_CIFR_OFFSET		0x28
+#define DTS_ICIFR_OFFSET	0x28
 
 /* DTS_CFGR1 register mask definitions */
 #define HSREF_CLK_DIV_MASK	GENMASK(30, 24)
@@ -122,10 +122,10 @@ static irqreturn_t stm_thermal_alarm_irq_thread(int irq, void *sdata)
 	value = readl_relaxed(sensor->base + DTS_SR_OFFSET);
 
 	if ((value & LOW_THRESHOLD) == LOW_THRESHOLD)
-		writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+		writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
 
 	if ((value & HIGH_THRESHOLD) == HIGH_THRESHOLD)
-		writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+		writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
 
 	thermal_zone_device_update(sensor->th_dev, THERMAL_EVENT_UNSPECIFIED);
 
@@ -347,7 +347,7 @@ static int stm_enable_irq(struct stm_thermal_sensor *sensor)
 	 */
 
 	/* Make sure LOW_THRESHOLD IT is clear before enabling */
-	writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+	writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
 
 	/* Enable IT generation for low threshold */
 	value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
@@ -356,7 +356,7 @@ static int stm_enable_irq(struct stm_thermal_sensor *sensor)
 	/* Enable the low temperature threshold if needed */
 	if (sensor->low_temp_enabled) {
 		/* Make sure HIGH_THRESHOLD IT is clear before enabling */
-		writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+		writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
 
 		/* Enable IT generation for high threshold */
 		value |= HIGH_THRESHOLD;
-- 
2.17.1


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  reply	other threads:[~2020-01-10 10:16 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-10 10:15 [PATCH_V3 0/6] thermal: stm32: driver improvements Pascal Paillet
2020-01-10 10:15 ` Pascal Paillet
2020-01-10 10:16 ` Pascal Paillet [this message]
2020-01-10 10:16   ` [PATCH_V3 1/6] thermal: stm32: fix icifr register name Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 2/6] thermal: stm32: rework sensor mode management Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 3/6] thermal: stm32: disable interrupts at probe Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 4/6] thermal: stm32: handle multiple trip points Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 5/6] thermal: stm32: improve temperature computing Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 6/6] thermal: stm32: fix low threshold interrupt flood Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-27 13:17 ` [PATCH_V3 0/6] thermal: stm32: driver improvements Pascal PAILLET-LME
2020-01-27 13:17   ` Pascal PAILLET-LME
2020-01-27 14:39   ` Daniel Lezcano
2020-01-27 14:39     ` Daniel Lezcano

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