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From: Pascal Paillet <p.paillet@st.com>
To: <rui.zhang@intel.com>, <edubezval@gmail.com>,
	<daniel.lezcano@linaro.org>, <amit.kucheria@verdurent.com>,
	<mcoquelin.stm32@gmail.com>, <alexandre.torgue@st.com>,
	<p.paillet@st.com>, <david.hernandezsanchez@st.com>,
	<horms+renesas@verge.net.au>, <wsa+renesas@sang-engineering.com>,
	<linux-pm@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH_V3 3/6] thermal: stm32: disable interrupts at probe
Date: Fri, 10 Jan 2020 11:16:02 +0100	[thread overview]
Message-ID: <20200110101605.24984-4-p.paillet@st.com> (raw)
In-Reply-To: <20200110101605.24984-1-p.paillet@st.com>

In case of CPU reset, the interrupts could be enabled at boot time.
Disable interrupts and clear flags.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
---
 drivers/thermal/st/stm_thermal.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/thermal/st/stm_thermal.c b/drivers/thermal/st/stm_thermal.c
index a21fa7e0c72b..679d38867206 100644
--- a/drivers/thermal/st/stm_thermal.c
+++ b/drivers/thermal/st/stm_thermal.c
@@ -51,6 +51,12 @@
 /* DTS_DR register mask definitions */
 #define TS1_MFREQ_MASK		GENMASK(15, 0)
 
+/* DTS_ITENR register mask definitions */
+#define ITENR_MASK		(GENMASK(2, 0) | GENMASK(6, 4))
+
+/* DTS_ICIFR register mask definitions */
+#define ICIFR_MASK		(GENMASK(2, 0) | GENMASK(6, 4))
+
 /* Less significant bit position definitions */
 #define TS1_T0_POS		16
 #define TS1_SMP_TIME_POS	16
@@ -330,12 +336,10 @@ static int stm_disable_irq(struct stm_thermal_sensor *sensor)
 {
 	u32 value;
 
-	/* Disable IT generation for low and high thresholds */
+	/* Disable IT generation */
 	value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
-	writel_relaxed(value & ~(LOW_THRESHOLD | HIGH_THRESHOLD),
-		       sensor->base + DTS_ITENR_OFFSET);
-
-	dev_dbg(sensor->dev, "%s: IT disabled on sensor side", __func__);
+	value &= ~ITENR_MASK;
+	writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
 
 	return 0;
 }
@@ -645,6 +649,11 @@ static int stm_thermal_probe(struct platform_device *pdev)
 		return PTR_ERR(sensor->clk);
 	}
 
+	stm_disable_irq(sensor);
+
+	/* Clear irq flags */
+	writel_relaxed(ICIFR_MASK, sensor->base + DTS_ICIFR_OFFSET);
+
 	/* Register IRQ into GIC */
 	ret = stm_register_irq(sensor);
 	if (ret)
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Pascal Paillet <p.paillet@st.com>
To: <rui.zhang@intel.com>, <edubezval@gmail.com>,
	<daniel.lezcano@linaro.org>,  <amit.kucheria@verdurent.com>,
	<mcoquelin.stm32@gmail.com>, <alexandre.torgue@st.com>,
	<p.paillet@st.com>, <david.hernandezsanchez@st.com>,
	<horms+renesas@verge.net.au>, <wsa+renesas@sang-engineering.com>,
	<linux-pm@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH_V3 3/6] thermal: stm32: disable interrupts at probe
Date: Fri, 10 Jan 2020 11:16:02 +0100	[thread overview]
Message-ID: <20200110101605.24984-4-p.paillet@st.com> (raw)
In-Reply-To: <20200110101605.24984-1-p.paillet@st.com>

In case of CPU reset, the interrupts could be enabled at boot time.
Disable interrupts and clear flags.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
---
 drivers/thermal/st/stm_thermal.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/thermal/st/stm_thermal.c b/drivers/thermal/st/stm_thermal.c
index a21fa7e0c72b..679d38867206 100644
--- a/drivers/thermal/st/stm_thermal.c
+++ b/drivers/thermal/st/stm_thermal.c
@@ -51,6 +51,12 @@
 /* DTS_DR register mask definitions */
 #define TS1_MFREQ_MASK		GENMASK(15, 0)
 
+/* DTS_ITENR register mask definitions */
+#define ITENR_MASK		(GENMASK(2, 0) | GENMASK(6, 4))
+
+/* DTS_ICIFR register mask definitions */
+#define ICIFR_MASK		(GENMASK(2, 0) | GENMASK(6, 4))
+
 /* Less significant bit position definitions */
 #define TS1_T0_POS		16
 #define TS1_SMP_TIME_POS	16
@@ -330,12 +336,10 @@ static int stm_disable_irq(struct stm_thermal_sensor *sensor)
 {
 	u32 value;
 
-	/* Disable IT generation for low and high thresholds */
+	/* Disable IT generation */
 	value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
-	writel_relaxed(value & ~(LOW_THRESHOLD | HIGH_THRESHOLD),
-		       sensor->base + DTS_ITENR_OFFSET);
-
-	dev_dbg(sensor->dev, "%s: IT disabled on sensor side", __func__);
+	value &= ~ITENR_MASK;
+	writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
 
 	return 0;
 }
@@ -645,6 +649,11 @@ static int stm_thermal_probe(struct platform_device *pdev)
 		return PTR_ERR(sensor->clk);
 	}
 
+	stm_disable_irq(sensor);
+
+	/* Clear irq flags */
+	writel_relaxed(ICIFR_MASK, sensor->base + DTS_ICIFR_OFFSET);
+
 	/* Register IRQ into GIC */
 	ret = stm_register_irq(sensor);
 	if (ret)
-- 
2.17.1


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  parent reply	other threads:[~2020-01-10 10:16 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-10 10:15 [PATCH_V3 0/6] thermal: stm32: driver improvements Pascal Paillet
2020-01-10 10:15 ` Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 1/6] thermal: stm32: fix icifr register name Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 2/6] thermal: stm32: rework sensor mode management Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-10 10:16 ` Pascal Paillet [this message]
2020-01-10 10:16   ` [PATCH_V3 3/6] thermal: stm32: disable interrupts at probe Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 4/6] thermal: stm32: handle multiple trip points Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 5/6] thermal: stm32: improve temperature computing Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-10 10:16 ` [PATCH_V3 6/6] thermal: stm32: fix low threshold interrupt flood Pascal Paillet
2020-01-10 10:16   ` Pascal Paillet
2020-01-27 13:17 ` [PATCH_V3 0/6] thermal: stm32: driver improvements Pascal PAILLET-LME
2020-01-27 13:17   ` Pascal PAILLET-LME
2020-01-27 14:39   ` Daniel Lezcano
2020-01-27 14:39     ` Daniel Lezcano

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