From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
Robert Richter <rrichter@marvell.com>,
Thomas Gleixner <tglx@linutronix.de>,
Zenghui Yu <yuzenghui@huawei.com>,
Eric Auger <eric.auger@redhat.com>,
James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support
Date: Wed, 4 Mar 2020 20:33:07 +0000 [thread overview]
Message-ID: <20200304203330.4967-1-maz@kernel.org> (raw)
This (now shorter) series expands the existing GICv4 support to deal
with the new GICv4.1 architecture, which comes with a set of major
improvements compared to v4.0:
- One architectural doorbell per vcpu, instead of one doorbell per VLPI
- Doorbell entirely managed by the HW, with an "at most once" delivery
guarantee per non-residency phase and only when requested by the
hypervisor
- A shared memory scheme between ITSs and redistributors, allowing for an
optimised residency sequence (the use of VMOVP becomes less frequent)
- Support for direct virtual SGI delivery (the injection path still involves
the hypervisor), at the cost of losing the active state on SGIs. It
shouldn't be a big deal, but some guest operating systems might notice
(Linux definitely won't care).
On the other hand, public documentation is not available yet, so that's a
bit annoying...
The series is roughly organised in 3 parts:
(0) Fixes
(1) v4.1 doorbell management
(2) Virtual SGI support
(3) Plumbing of virtual SGIs in KVM
Notes:
- The whole thing is tested on a FVP model, which can be obtained
free of charge on ARM's developer website. It requires you to
create an account, unfortunately... You'll need a fix for the
devicetree that is in the kernel tree (should be merged before
the 5.6 release).
- This series has uncovered a behaviour that looks like a HW bug on
the Cavium ThunderX (aka TX1) platform. I'd very much welcome some
clarification from the Marvell/Cavium folks on Cc, as well as an
official erratum number if this happens to be an actual bug.
[v3 update]
People have ignored for two months now, and it is fairly obvious
that support for this machine is slowly bit-rotting. Maybe I'll
drop the patch and instead start the process of removing all TX1
support from the kernel (we'd certainly be better off without it).
[v4 update]
TX1 is now broken in mainline, and nobody cares. Make of this what
you want.
- I'm extremely grateful for Zenghui Yu's huge effort in carefully
reviewing this rather difficult series (if we ever get to meet
face to face, drinks are definitely on me!).
- Unless someone cries wolf, I plan to take this into 5.7.
* From v4 [4]
- Rebased on v5.6-rc4
- Fixed locking all over the shop now that we can bypass the ITS
- Wait on INVALL at the RD level
- Plentu of cleanups/fixes thanks to Zenghui's careful review effort
* From v3 [3]:
- Rebased on v5.6-rc1
- Considerably smaller thanks to the initial patches being merged
- Small bug fix after the v5.6 merge window
* From v2 [2]:
- Another bunch of fixes thanks to Zenghui Yu's very careful review
- HW-accelerated SGIs are now optional thanks to new architected
discovery/selection bits exposed by KVM and used by the guest kernel
- Rebased on v5.5-rc2
* From v1 [1]:
- A bunch of minor reworks after Zenghui Yu's review
- A workaround for what looks like a new and unexpected TX1 bug
- A subtle reorder of the series so that some patches can go in early
[1] https://lore.kernel.org/lkml/20190923182606.32100-1-maz@kernel.org/
[2] https://lore.kernel.org/lkml/20191027144234.8395-1-maz@kernel.org/
[3] https://lore.kernel.org/r/20191224111055.11836-1-maz@kernel.org/
[4] https://lore.kernel.org/r/20200214145736.18550-1-maz@kernel.org/
Marc Zyngier (22):
irqchip/gic-v3: Use SGIs without active state if offered
irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors
irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change
and RD access
irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the
same RD
irqchip/gic-v4.1: Advertise support v4.1 to KVM
irqchip/gic-v4.1: Map the ITS SGIR register page
irqchip/gic-v4.1: Plumb skeletal VSGI irqchip
irqchip/gic-v4.1: Add initial SGI configuration
irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks
irqchip/gic-v4.1: Plumb get/set_irqchip_state SGI callbacks
irqchip/gic-v4.1: Plumb set_vcpu_affinity SGI callbacks
irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction
layer
irqchip/gic-v4.1: Add VSGI allocation/teardown
irqchip/gic-v4.1: Add VSGI property setup
irqchip/gic-v4.1: Eagerly vmap vPEs
KVM: arm64: GICv4.1: Let doorbells be auto-enabled
KVM: arm64: GICv4.1: Add direct injection capability to SGI registers
KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts
KVM: arm64: GICv4.1: Plumb SGI implementation selection in the
distributor
KVM: arm64: GICv4.1: Reload VLPI configuration on distributor
enable/disable
KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs
KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs
Zenghui Yu (1):
irqchip/gic-v4.1: Wait for completion of redistributor's INVALL
operation
arch/arm/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/kvm_emulate.h | 3 +-
arch/arm64/include/asm/kvm_host.h | 1 +
drivers/irqchip/irq-gic-v3-its.c | 385 +++++++++++++++++++++++--
drivers/irqchip/irq-gic-v3.c | 13 +-
drivers/irqchip/irq-gic-v4.c | 134 ++++++++-
include/kvm/arm_vgic.h | 4 +
include/linux/irqchip/arm-gic-common.h | 2 +
include/linux/irqchip/arm-gic-v3.h | 20 +-
include/linux/irqchip/arm-gic-v4.h | 25 +-
virt/kvm/arm/arm.c | 8 +
virt/kvm/arm/vgic/vgic-debug.c | 14 +-
virt/kvm/arm/vgic/vgic-mmio-v3.c | 68 ++++-
virt/kvm/arm/vgic/vgic-mmio.c | 88 +++++-
virt/kvm/arm/vgic/vgic-v3.c | 6 +-
virt/kvm/arm/vgic/vgic-v4.c | 137 +++++++--
virt/kvm/arm/vgic/vgic.h | 1 +
17 files changed, 844 insertions(+), 66 deletions(-)
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
Robert Richter <rrichter@marvell.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support
Date: Wed, 4 Mar 2020 20:33:07 +0000 [thread overview]
Message-ID: <20200304203330.4967-1-maz@kernel.org> (raw)
This (now shorter) series expands the existing GICv4 support to deal
with the new GICv4.1 architecture, which comes with a set of major
improvements compared to v4.0:
- One architectural doorbell per vcpu, instead of one doorbell per VLPI
- Doorbell entirely managed by the HW, with an "at most once" delivery
guarantee per non-residency phase and only when requested by the
hypervisor
- A shared memory scheme between ITSs and redistributors, allowing for an
optimised residency sequence (the use of VMOVP becomes less frequent)
- Support for direct virtual SGI delivery (the injection path still involves
the hypervisor), at the cost of losing the active state on SGIs. It
shouldn't be a big deal, but some guest operating systems might notice
(Linux definitely won't care).
On the other hand, public documentation is not available yet, so that's a
bit annoying...
The series is roughly organised in 3 parts:
(0) Fixes
(1) v4.1 doorbell management
(2) Virtual SGI support
(3) Plumbing of virtual SGIs in KVM
Notes:
- The whole thing is tested on a FVP model, which can be obtained
free of charge on ARM's developer website. It requires you to
create an account, unfortunately... You'll need a fix for the
devicetree that is in the kernel tree (should be merged before
the 5.6 release).
- This series has uncovered a behaviour that looks like a HW bug on
the Cavium ThunderX (aka TX1) platform. I'd very much welcome some
clarification from the Marvell/Cavium folks on Cc, as well as an
official erratum number if this happens to be an actual bug.
[v3 update]
People have ignored for two months now, and it is fairly obvious
that support for this machine is slowly bit-rotting. Maybe I'll
drop the patch and instead start the process of removing all TX1
support from the kernel (we'd certainly be better off without it).
[v4 update]
TX1 is now broken in mainline, and nobody cares. Make of this what
you want.
- I'm extremely grateful for Zenghui Yu's huge effort in carefully
reviewing this rather difficult series (if we ever get to meet
face to face, drinks are definitely on me!).
- Unless someone cries wolf, I plan to take this into 5.7.
* From v4 [4]
- Rebased on v5.6-rc4
- Fixed locking all over the shop now that we can bypass the ITS
- Wait on INVALL at the RD level
- Plentu of cleanups/fixes thanks to Zenghui's careful review effort
* From v3 [3]:
- Rebased on v5.6-rc1
- Considerably smaller thanks to the initial patches being merged
- Small bug fix after the v5.6 merge window
* From v2 [2]:
- Another bunch of fixes thanks to Zenghui Yu's very careful review
- HW-accelerated SGIs are now optional thanks to new architected
discovery/selection bits exposed by KVM and used by the guest kernel
- Rebased on v5.5-rc2
* From v1 [1]:
- A bunch of minor reworks after Zenghui Yu's review
- A workaround for what looks like a new and unexpected TX1 bug
- A subtle reorder of the series so that some patches can go in early
[1] https://lore.kernel.org/lkml/20190923182606.32100-1-maz@kernel.org/
[2] https://lore.kernel.org/lkml/20191027144234.8395-1-maz@kernel.org/
[3] https://lore.kernel.org/r/20191224111055.11836-1-maz@kernel.org/
[4] https://lore.kernel.org/r/20200214145736.18550-1-maz@kernel.org/
Marc Zyngier (22):
irqchip/gic-v3: Use SGIs without active state if offered
irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors
irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change
and RD access
irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the
same RD
irqchip/gic-v4.1: Advertise support v4.1 to KVM
irqchip/gic-v4.1: Map the ITS SGIR register page
irqchip/gic-v4.1: Plumb skeletal VSGI irqchip
irqchip/gic-v4.1: Add initial SGI configuration
irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks
irqchip/gic-v4.1: Plumb get/set_irqchip_state SGI callbacks
irqchip/gic-v4.1: Plumb set_vcpu_affinity SGI callbacks
irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction
layer
irqchip/gic-v4.1: Add VSGI allocation/teardown
irqchip/gic-v4.1: Add VSGI property setup
irqchip/gic-v4.1: Eagerly vmap vPEs
KVM: arm64: GICv4.1: Let doorbells be auto-enabled
KVM: arm64: GICv4.1: Add direct injection capability to SGI registers
KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts
KVM: arm64: GICv4.1: Plumb SGI implementation selection in the
distributor
KVM: arm64: GICv4.1: Reload VLPI configuration on distributor
enable/disable
KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs
KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs
Zenghui Yu (1):
irqchip/gic-v4.1: Wait for completion of redistributor's INVALL
operation
arch/arm/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/kvm_emulate.h | 3 +-
arch/arm64/include/asm/kvm_host.h | 1 +
drivers/irqchip/irq-gic-v3-its.c | 385 +++++++++++++++++++++++--
drivers/irqchip/irq-gic-v3.c | 13 +-
drivers/irqchip/irq-gic-v4.c | 134 ++++++++-
include/kvm/arm_vgic.h | 4 +
include/linux/irqchip/arm-gic-common.h | 2 +
include/linux/irqchip/arm-gic-v3.h | 20 +-
include/linux/irqchip/arm-gic-v4.h | 25 +-
virt/kvm/arm/arm.c | 8 +
virt/kvm/arm/vgic/vgic-debug.c | 14 +-
virt/kvm/arm/vgic/vgic-mmio-v3.c | 68 ++++-
virt/kvm/arm/vgic/vgic-mmio.c | 88 +++++-
virt/kvm/arm/vgic/vgic-v3.c | 6 +-
virt/kvm/arm/vgic/vgic-v4.c | 137 +++++++--
virt/kvm/arm/vgic/vgic.h | 1 +
17 files changed, 844 insertions(+), 66 deletions(-)
--
2.20.1
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Eric Auger <eric.auger@redhat.com>,
Robert Richter <rrichter@marvell.com>,
James Morse <james.morse@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Thomas Gleixner <tglx@linutronix.de>,
Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support
Date: Wed, 4 Mar 2020 20:33:07 +0000 [thread overview]
Message-ID: <20200304203330.4967-1-maz@kernel.org> (raw)
This (now shorter) series expands the existing GICv4 support to deal
with the new GICv4.1 architecture, which comes with a set of major
improvements compared to v4.0:
- One architectural doorbell per vcpu, instead of one doorbell per VLPI
- Doorbell entirely managed by the HW, with an "at most once" delivery
guarantee per non-residency phase and only when requested by the
hypervisor
- A shared memory scheme between ITSs and redistributors, allowing for an
optimised residency sequence (the use of VMOVP becomes less frequent)
- Support for direct virtual SGI delivery (the injection path still involves
the hypervisor), at the cost of losing the active state on SGIs. It
shouldn't be a big deal, but some guest operating systems might notice
(Linux definitely won't care).
On the other hand, public documentation is not available yet, so that's a
bit annoying...
The series is roughly organised in 3 parts:
(0) Fixes
(1) v4.1 doorbell management
(2) Virtual SGI support
(3) Plumbing of virtual SGIs in KVM
Notes:
- The whole thing is tested on a FVP model, which can be obtained
free of charge on ARM's developer website. It requires you to
create an account, unfortunately... You'll need a fix for the
devicetree that is in the kernel tree (should be merged before
the 5.6 release).
- This series has uncovered a behaviour that looks like a HW bug on
the Cavium ThunderX (aka TX1) platform. I'd very much welcome some
clarification from the Marvell/Cavium folks on Cc, as well as an
official erratum number if this happens to be an actual bug.
[v3 update]
People have ignored for two months now, and it is fairly obvious
that support for this machine is slowly bit-rotting. Maybe I'll
drop the patch and instead start the process of removing all TX1
support from the kernel (we'd certainly be better off without it).
[v4 update]
TX1 is now broken in mainline, and nobody cares. Make of this what
you want.
- I'm extremely grateful for Zenghui Yu's huge effort in carefully
reviewing this rather difficult series (if we ever get to meet
face to face, drinks are definitely on me!).
- Unless someone cries wolf, I plan to take this into 5.7.
* From v4 [4]
- Rebased on v5.6-rc4
- Fixed locking all over the shop now that we can bypass the ITS
- Wait on INVALL at the RD level
- Plentu of cleanups/fixes thanks to Zenghui's careful review effort
* From v3 [3]:
- Rebased on v5.6-rc1
- Considerably smaller thanks to the initial patches being merged
- Small bug fix after the v5.6 merge window
* From v2 [2]:
- Another bunch of fixes thanks to Zenghui Yu's very careful review
- HW-accelerated SGIs are now optional thanks to new architected
discovery/selection bits exposed by KVM and used by the guest kernel
- Rebased on v5.5-rc2
* From v1 [1]:
- A bunch of minor reworks after Zenghui Yu's review
- A workaround for what looks like a new and unexpected TX1 bug
- A subtle reorder of the series so that some patches can go in early
[1] https://lore.kernel.org/lkml/20190923182606.32100-1-maz@kernel.org/
[2] https://lore.kernel.org/lkml/20191027144234.8395-1-maz@kernel.org/
[3] https://lore.kernel.org/r/20191224111055.11836-1-maz@kernel.org/
[4] https://lore.kernel.org/r/20200214145736.18550-1-maz@kernel.org/
Marc Zyngier (22):
irqchip/gic-v3: Use SGIs without active state if offered
irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors
irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change
and RD access
irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the
same RD
irqchip/gic-v4.1: Advertise support v4.1 to KVM
irqchip/gic-v4.1: Map the ITS SGIR register page
irqchip/gic-v4.1: Plumb skeletal VSGI irqchip
irqchip/gic-v4.1: Add initial SGI configuration
irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks
irqchip/gic-v4.1: Plumb get/set_irqchip_state SGI callbacks
irqchip/gic-v4.1: Plumb set_vcpu_affinity SGI callbacks
irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction
layer
irqchip/gic-v4.1: Add VSGI allocation/teardown
irqchip/gic-v4.1: Add VSGI property setup
irqchip/gic-v4.1: Eagerly vmap vPEs
KVM: arm64: GICv4.1: Let doorbells be auto-enabled
KVM: arm64: GICv4.1: Add direct injection capability to SGI registers
KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts
KVM: arm64: GICv4.1: Plumb SGI implementation selection in the
distributor
KVM: arm64: GICv4.1: Reload VLPI configuration on distributor
enable/disable
KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs
KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs
Zenghui Yu (1):
irqchip/gic-v4.1: Wait for completion of redistributor's INVALL
operation
arch/arm/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/kvm_emulate.h | 3 +-
arch/arm64/include/asm/kvm_host.h | 1 +
drivers/irqchip/irq-gic-v3-its.c | 385 +++++++++++++++++++++++--
drivers/irqchip/irq-gic-v3.c | 13 +-
drivers/irqchip/irq-gic-v4.c | 134 ++++++++-
include/kvm/arm_vgic.h | 4 +
include/linux/irqchip/arm-gic-common.h | 2 +
include/linux/irqchip/arm-gic-v3.h | 20 +-
include/linux/irqchip/arm-gic-v4.h | 25 +-
virt/kvm/arm/arm.c | 8 +
virt/kvm/arm/vgic/vgic-debug.c | 14 +-
virt/kvm/arm/vgic/vgic-mmio-v3.c | 68 ++++-
virt/kvm/arm/vgic/vgic-mmio.c | 88 +++++-
virt/kvm/arm/vgic/vgic-v3.c | 6 +-
virt/kvm/arm/vgic/vgic-v4.c | 137 +++++++--
virt/kvm/arm/vgic/vgic.h | 1 +
17 files changed, 844 insertions(+), 66 deletions(-)
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2020-03-04 20:34 UTC|newest]
Thread overview: 312+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-04 20:33 Marc Zyngier [this message]
2020-03-04 20:33 ` [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 01/23] irqchip/gic-v3: Use SGIs without active state if offered Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 6:30 ` Zenghui Yu
2020-03-12 6:30 ` Zenghui Yu
2020-03-12 6:30 ` Zenghui Yu
2020-03-12 9:28 ` Marc Zyngier
2020-03-12 9:28 ` Marc Zyngier
2020-03-12 9:28 ` Marc Zyngier
2020-03-12 12:05 ` Marc Zyngier
2020-03-12 12:05 ` Marc Zyngier
2020-03-12 12:05 ` Marc Zyngier
2020-03-13 1:39 ` Zenghui Yu
2020-03-13 1:39 ` Zenghui Yu
2020-03-13 1:39 ` Zenghui Yu
2020-03-12 17:16 ` Auger Eric
2020-03-12 17:16 ` Auger Eric
2020-03-12 17:16 ` Auger Eric
2020-03-12 17:23 ` Marc Zyngier
2020-03-12 17:23 ` Marc Zyngier
2020-03-12 17:23 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 02/23] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-16 17:10 ` Auger Eric
2020-03-16 17:10 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 03/23] irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 6:56 ` Zenghui Yu
2020-03-12 6:56 ` Zenghui Yu
2020-03-12 6:56 ` Zenghui Yu
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 04/23] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-20 14:23 ` Auger Eric
2020-03-20 14:23 ` Auger Eric
2020-03-20 14:23 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 05/23] irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the same RD Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 7:11 ` Zenghui Yu
2020-03-12 7:11 ` Zenghui Yu
2020-03-12 7:11 ` Zenghui Yu
2020-03-20 14:23 ` Auger Eric
2020-03-20 14:23 ` Auger Eric
2020-03-20 14:23 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 06/23] irqchip/gic-v4.1: Advertise support v4.1 to KVM Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-16 17:10 ` Auger Eric
2020-03-16 17:10 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 07/23] irqchip/gic-v4.1: Map the ITS SGIR register page Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-16 17:10 ` Auger Eric
2020-03-16 17:10 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 08/23] irqchip/gic-v4.1: Plumb skeletal VSGI irqchip Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-16 17:10 ` Auger Eric
2020-03-16 17:10 ` Auger Eric
2020-03-19 10:03 ` Marc Zyngier
2020-03-19 10:03 ` Marc Zyngier
2020-03-19 10:03 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 09/23] irqchip/gic-v4.1: Add initial SGI configuration Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-16 17:53 ` Auger Eric
2020-03-16 17:53 ` Auger Eric
2020-03-16 17:53 ` Auger Eric
2020-03-17 2:02 ` Zenghui Yu
2020-03-17 2:02 ` Zenghui Yu
2020-03-17 2:02 ` Zenghui Yu
2020-03-17 8:36 ` Auger Eric
2020-03-17 8:36 ` Auger Eric
2020-03-17 8:36 ` Auger Eric
2020-03-19 10:20 ` Marc Zyngier
2020-03-19 10:20 ` Marc Zyngier
2020-03-19 10:20 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 10/23] irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-16 18:15 ` Auger Eric
2020-03-16 18:15 ` Auger Eric
2020-03-16 18:15 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 11/23] irqchip/gic-v4.1: Plumb get/set_irqchip_state " Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 7:41 ` Zenghui Yu
2020-03-12 7:41 ` Zenghui Yu
2020-03-12 7:41 ` Zenghui Yu
2020-03-16 21:43 ` Auger Eric
2020-03-16 21:43 ` Auger Eric
2020-03-16 21:43 ` Auger Eric
2020-03-19 10:27 ` Marc Zyngier
2020-03-19 10:27 ` Marc Zyngier
2020-03-19 10:27 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 12/23] irqchip/gic-v4.1: Plumb set_vcpu_affinity " Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-17 10:35 ` Auger Eric
2020-03-17 10:35 ` Auger Eric
2020-03-17 10:35 ` Auger Eric
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 13/23] irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 8:20 ` Zenghui Yu
2020-03-12 8:20 ` Zenghui Yu
2020-03-12 8:20 ` Zenghui Yu
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 14/23] irqchip/gic-v4.1: Add VSGI allocation/teardown Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 8:06 ` Zenghui Yu
2020-03-12 8:06 ` Zenghui Yu
2020-03-12 8:06 ` Zenghui Yu
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 15/23] irqchip/gic-v4.1: Add VSGI property setup Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 8:09 ` Zenghui Yu
2020-03-12 8:09 ` Zenghui Yu
2020-03-12 8:09 ` Zenghui Yu
2020-03-17 10:30 ` Auger Eric
2020-03-17 10:30 ` Auger Eric
2020-03-17 10:30 ` Auger Eric
2020-03-19 10:57 ` Marc Zyngier
2020-03-19 10:57 ` Marc Zyngier
2020-03-19 10:57 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 16/23] irqchip/gic-v4.1: Eagerly vmap vPEs Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 8:12 ` Zenghui Yu
2020-03-12 8:12 ` Zenghui Yu
2020-03-12 8:12 ` Zenghui Yu
2020-03-17 2:49 ` Zenghui Yu
2020-03-17 2:49 ` Zenghui Yu
2020-03-17 2:49 ` Zenghui Yu
2020-03-19 10:55 ` Marc Zyngier
2020-03-19 10:55 ` Marc Zyngier
2020-03-19 10:55 ` Marc Zyngier
2020-03-20 2:31 ` Zenghui Yu
2020-03-20 2:31 ` Zenghui Yu
2020-03-20 2:31 ` Zenghui Yu
2020-03-29 20:26 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 17/23] KVM: arm64: GICv4.1: Let doorbells be auto-enabled Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-12 8:15 ` Zenghui Yu
2020-03-12 8:15 ` Zenghui Yu
2020-03-12 8:15 ` Zenghui Yu
2020-03-17 11:04 ` Auger Eric
2020-03-17 11:04 ` Auger Eric
2020-03-17 11:04 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 18/23] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-18 3:28 ` Zenghui Yu
2020-03-18 3:28 ` Zenghui Yu
2020-03-18 3:28 ` Zenghui Yu
2020-03-20 8:11 ` Auger Eric
2020-03-20 8:11 ` Auger Eric
2020-03-20 8:11 ` Auger Eric
2020-03-20 10:05 ` Marc Zyngier
2020-03-20 10:05 ` Marc Zyngier
2020-03-20 10:05 ` Marc Zyngier
2020-03-20 10:56 ` Auger Eric
2020-03-20 10:56 ` Auger Eric
2020-03-20 10:56 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 19/23] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-19 16:16 ` Auger Eric
2020-03-19 16:16 ` Auger Eric
2020-03-19 16:16 ` Auger Eric
2020-03-19 19:52 ` Marc Zyngier
2020-03-19 19:52 ` Marc Zyngier
2020-03-19 19:52 ` Marc Zyngier
2020-03-19 20:13 ` Auger Eric
2020-03-19 20:13 ` Auger Eric
2020-03-19 20:13 ` Auger Eric
2020-03-20 9:17 ` Marc Zyngier
2020-03-20 9:17 ` Marc Zyngier
2020-03-20 9:17 ` Marc Zyngier
2020-03-20 4:22 ` Zenghui Yu
2020-03-20 4:22 ` Zenghui Yu
2020-03-20 4:22 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 20/23] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-18 6:34 ` Zenghui Yu
2020-03-18 6:34 ` Zenghui Yu
2020-03-18 6:34 ` Zenghui Yu
2020-03-19 12:10 ` Marc Zyngier
2020-03-19 12:10 ` Marc Zyngier
2020-03-19 12:10 ` Marc Zyngier
2020-03-19 20:38 ` Auger Eric
2020-03-19 20:38 ` Auger Eric
2020-03-19 20:38 ` Auger Eric
2020-03-20 3:08 ` Zenghui Yu
2020-03-20 3:08 ` Zenghui Yu
2020-03-20 3:08 ` Zenghui Yu
2020-03-20 7:59 ` Auger Eric
2020-03-20 7:59 ` Auger Eric
2020-03-20 7:59 ` Auger Eric
2020-03-20 9:46 ` Marc Zyngier
2020-03-20 9:46 ` Marc Zyngier
2020-03-20 9:46 ` Marc Zyngier
2020-03-20 11:09 ` Auger Eric
2020-03-20 11:09 ` Auger Eric
2020-03-20 11:09 ` Auger Eric
2020-03-20 11:20 ` Marc Zyngier
2020-03-20 11:20 ` Marc Zyngier
2020-03-20 11:20 ` Marc Zyngier
2020-03-20 3:53 ` Zenghui Yu
2020-03-20 3:53 ` Zenghui Yu
2020-03-20 3:53 ` Zenghui Yu
2020-03-20 9:01 ` Marc Zyngier
2020-03-20 9:01 ` Marc Zyngier
2020-03-20 9:01 ` Marc Zyngier
2020-03-23 8:11 ` Zenghui Yu
2020-03-23 8:11 ` Zenghui Yu
2020-03-23 8:11 ` Zenghui Yu
2020-03-23 8:25 ` Marc Zyngier
2020-03-23 8:25 ` Marc Zyngier
2020-03-23 8:25 ` Marc Zyngier
2020-03-23 12:40 ` Zenghui Yu
2020-03-23 12:40 ` Zenghui Yu
2020-03-23 12:40 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 21/23] KVM: arm64: GICv4.1: Reload VLPI configuration on distributor enable/disable Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-18 3:17 ` Zenghui Yu
2020-03-18 3:17 ` Zenghui Yu
2020-03-18 3:17 ` Zenghui Yu
2020-03-19 12:18 ` Marc Zyngier
2020-03-19 12:18 ` Marc Zyngier
2020-03-19 12:18 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 22/23] KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-20 4:23 ` Zenghui Yu
2020-03-20 4:23 ` Zenghui Yu
2020-03-20 4:23 ` Zenghui Yu
2020-03-20 8:12 ` Auger Eric
2020-03-20 8:12 ` Auger Eric
2020-03-20 8:12 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 23/23] KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-04 20:33 ` Marc Zyngier
2020-03-18 3:19 ` Zenghui Yu
2020-03-18 3:19 ` Zenghui Yu
2020-03-18 3:19 ` Zenghui Yu
2020-03-19 15:05 ` Auger Eric
2020-03-19 15:05 ` Auger Eric
2020-03-19 15:05 ` Auger Eric
2020-03-19 15:21 ` Marc Zyngier
2020-03-19 15:21 ` Marc Zyngier
2020-03-19 15:21 ` Marc Zyngier
2020-03-19 15:43 ` Auger Eric
2020-03-19 15:43 ` Auger Eric
2020-03-19 15:43 ` Auger Eric
2020-03-19 16:16 ` Marc Zyngier
2020-03-19 16:16 ` Marc Zyngier
2020-03-19 16:16 ` Marc Zyngier
2020-03-19 16:17 ` Auger Eric
2020-03-19 16:17 ` Auger Eric
2020-03-19 16:17 ` Auger Eric
2020-03-20 4:38 ` Zenghui Yu
2020-03-20 4:38 ` Zenghui Yu
2020-03-20 4:38 ` Zenghui Yu
2020-03-20 9:09 ` Marc Zyngier
2020-03-20 9:09 ` Marc Zyngier
2020-03-20 9:09 ` Marc Zyngier
2020-03-20 11:35 ` Zenghui Yu
2020-03-20 11:35 ` Zenghui Yu
2020-03-20 11:35 ` Zenghui Yu
2020-03-20 11:46 ` Marc Zyngier
2020-03-20 11:46 ` Marc Zyngier
2020-03-20 11:46 ` Marc Zyngier
2020-03-20 12:09 ` Zenghui Yu
2020-03-20 12:09 ` Zenghui Yu
2020-03-20 12:09 ` Zenghui Yu
2020-03-05 3:39 ` [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support Zenghui Yu
2020-03-05 3:39 ` Zenghui Yu
2020-03-05 3:39 ` Zenghui Yu
2020-03-09 8:17 ` Zenghui Yu
2020-03-09 8:17 ` Zenghui Yu
2020-03-09 8:17 ` Zenghui Yu
2020-03-09 8:46 ` Marc Zyngier
2020-03-09 8:46 ` Marc Zyngier
2020-03-09 8:46 ` Marc Zyngier
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