From: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: "Thierry Reding"
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"Jonathan Hunter"
<jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
"Artur Świgoń" <a.swigon-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
"Georgi Djakov"
<georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
"Rob Herring" <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v2 09/22] ARM: tegra: Add interconnect properties to Tegra30 device-tree
Date: Mon, 30 Mar 2020 04:08:51 +0300 [thread overview]
Message-ID: <20200330010904.27643-10-digetx@gmail.com> (raw)
In-Reply-To: <20200330010904.27643-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Add interconnect properties to the memory controller, external memory
controller and the display controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/tegra30.dtsi | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index d2d05f1da274..2b183025629f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -208,6 +208,15 @@ dc@54200000 {
nvidia,head = <0>;
+ interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
+ <&mc TEGRA30_MC_DISPLAY0B &emc>,
+ <&mc TEGRA30_MC_DISPLAY0C &emc>,
+ <&mc TEGRA30_MC_DISPLAY1B &emc>;
+ interconnect-names = "display0a",
+ "display0b",
+ "display0c",
+ "display1b";
+
rgb {
status = "disabled";
};
@@ -227,6 +236,15 @@ dc@54240000 {
nvidia,head = <1>;
+ interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
+ <&mc TEGRA30_MC_DISPLAY0BB &emc>,
+ <&mc TEGRA30_MC_DISPLAY0CB &emc>,
+ <&mc TEGRA30_MC_DISPLAY1BB &emc>;
+ interconnect-names = "display0a",
+ "display0b",
+ "display0c",
+ "display1b";
+
rgb {
status = "disabled";
};
@@ -733,15 +751,18 @@ mc: memory-controller@7000f000 {
#iommu-cells = <1>;
#reset-cells = <1>;
+ #interconnect-cells = <1>;
};
- memory-controller@7000f400 {
+ emc: memory-controller@7000f400 {
compatible = "nvidia,tegra30-emc";
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_EMC>;
nvidia,memory-controller = <&mc>;
+
+ #interconnect-cells = <0>;
};
fuse@7000f800 {
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Artur Świgoń" <a.swigon@samsung.com>,
"Georgi Djakov" <georgi.djakov@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>
Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org
Subject: [PATCH v2 09/22] ARM: tegra: Add interconnect properties to Tegra30 device-tree
Date: Mon, 30 Mar 2020 04:08:51 +0300 [thread overview]
Message-ID: <20200330010904.27643-10-digetx@gmail.com> (raw)
In-Reply-To: <20200330010904.27643-1-digetx@gmail.com>
Add interconnect properties to the memory controller, external memory
controller and the display controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra30.dtsi | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index d2d05f1da274..2b183025629f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -208,6 +208,15 @@ dc@54200000 {
nvidia,head = <0>;
+ interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
+ <&mc TEGRA30_MC_DISPLAY0B &emc>,
+ <&mc TEGRA30_MC_DISPLAY0C &emc>,
+ <&mc TEGRA30_MC_DISPLAY1B &emc>;
+ interconnect-names = "display0a",
+ "display0b",
+ "display0c",
+ "display1b";
+
rgb {
status = "disabled";
};
@@ -227,6 +236,15 @@ dc@54240000 {
nvidia,head = <1>;
+ interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
+ <&mc TEGRA30_MC_DISPLAY0BB &emc>,
+ <&mc TEGRA30_MC_DISPLAY0CB &emc>,
+ <&mc TEGRA30_MC_DISPLAY1BB &emc>;
+ interconnect-names = "display0a",
+ "display0b",
+ "display0c",
+ "display1b";
+
rgb {
status = "disabled";
};
@@ -733,15 +751,18 @@ mc: memory-controller@7000f000 {
#iommu-cells = <1>;
#reset-cells = <1>;
+ #interconnect-cells = <1>;
};
- memory-controller@7000f400 {
+ emc: memory-controller@7000f400 {
compatible = "nvidia,tegra30-emc";
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_EMC>;
nvidia,memory-controller = <&mc>;
+
+ #interconnect-cells = <0>;
};
fuse@7000f800 {
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Artur Świgoń" <a.swigon@samsung.com>,
"Georgi Djakov" <georgi.djakov@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-pm@vger.kernel.org
Subject: [PATCH v2 09/22] ARM: tegra: Add interconnect properties to Tegra30 device-tree
Date: Mon, 30 Mar 2020 04:08:51 +0300 [thread overview]
Message-ID: <20200330010904.27643-10-digetx@gmail.com> (raw)
In-Reply-To: <20200330010904.27643-1-digetx@gmail.com>
Add interconnect properties to the memory controller, external memory
controller and the display controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra30.dtsi | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index d2d05f1da274..2b183025629f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -208,6 +208,15 @@ dc@54200000 {
nvidia,head = <0>;
+ interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
+ <&mc TEGRA30_MC_DISPLAY0B &emc>,
+ <&mc TEGRA30_MC_DISPLAY0C &emc>,
+ <&mc TEGRA30_MC_DISPLAY1B &emc>;
+ interconnect-names = "display0a",
+ "display0b",
+ "display0c",
+ "display1b";
+
rgb {
status = "disabled";
};
@@ -227,6 +236,15 @@ dc@54240000 {
nvidia,head = <1>;
+ interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
+ <&mc TEGRA30_MC_DISPLAY0BB &emc>,
+ <&mc TEGRA30_MC_DISPLAY0CB &emc>,
+ <&mc TEGRA30_MC_DISPLAY1BB &emc>;
+ interconnect-names = "display0a",
+ "display0b",
+ "display0c",
+ "display1b";
+
rgb {
status = "disabled";
};
@@ -733,15 +751,18 @@ mc: memory-controller@7000f000 {
#iommu-cells = <1>;
#reset-cells = <1>;
+ #interconnect-cells = <1>;
};
- memory-controller@7000f400 {
+ emc: memory-controller@7000f400 {
compatible = "nvidia,tegra30-emc";
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_EMC>;
nvidia,memory-controller = <&mc>;
+
+ #interconnect-cells = <0>;
};
fuse@7000f800 {
--
2.25.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-03-30 1:08 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 1:08 [PATCH v2 00/22] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 01/22] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-04-10 17:05 ` Rob Herring
2020-04-10 17:05 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 02/22] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
[not found] ` <20200330010904.27643-3-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-04-10 17:06 ` Rob Herring
2020-04-10 17:06 ` Rob Herring
2020-04-10 17:06 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 03/22] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
[not found] ` <20200330010904.27643-4-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-04-10 17:06 ` Rob Herring
2020-04-10 17:06 ` Rob Herring
2020-04-10 17:06 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 06/22] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
[not found] ` <20200330010904.27643-7-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-04-10 17:10 ` Rob Herring
2020-04-10 17:10 ` Rob Herring
2020-04-10 17:10 ` Rob Herring
[not found] ` <20200330010904.27643-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-30 1:08 ` [PATCH v2 04/22] dt-bindings: memory: tegra30: emc: Document new interconnect property Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
[not found] ` <20200330010904.27643-5-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-04-10 17:07 ` Rob Herring
2020-04-10 17:07 ` Rob Herring
2020-04-10 17:07 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 05/22] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
[not found] ` <20200330010904.27643-6-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-04-10 17:09 ` Rob Herring
2020-04-10 17:09 ` Rob Herring
2020-04-10 17:09 ` Rob Herring
2020-04-10 18:28 ` Dmitry Osipenko
2020-04-10 18:28 ` Dmitry Osipenko
2020-04-10 18:28 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 07/22] dt-bindings: memory: tegra30: Add memory client IDs Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
[not found] ` <20200330010904.27643-8-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-04-10 17:10 ` Rob Herring
2020-04-10 17:10 ` Rob Herring
2020-04-10 17:10 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 08/22] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko [this message]
2020-03-30 1:08 ` [PATCH v2 09/22] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 13/22] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 16/22] memory: tegra30-emc: " Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 17/22] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
[not found] ` <20200330010904.27643-18-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-04-13 12:44 ` Georgi Djakov
2020-04-13 12:44 ` Georgi Djakov
2020-04-13 12:44 ` Georgi Djakov
[not found] ` <d8e39d8b-b3f3-4a30-cb5a-67fcbe18a957-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2020-04-13 15:18 ` Dmitry Osipenko
2020-04-13 15:18 ` Dmitry Osipenko
2020-04-13 15:18 ` Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 19/22] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 20/22] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 21/22] ARM: tegra: Enable interconnect API in tegra_defconfig Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 22/22] ARM: multi_v7_defconfig: Enable interconnect API Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 10/22] interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 11/22] memory: tegra: Register as interconnect provider Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
[not found] ` <20200330010904.27643-12-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-04-13 12:43 ` Georgi Djakov
2020-04-13 12:43 ` Georgi Djakov
2020-04-13 12:43 ` Georgi Djakov
[not found] ` <70f724d6-5cb2-0ebe-ffc1-5dbb77d9dc74-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2020-04-13 15:01 ` Dmitry Osipenko
2020-04-13 15:01 ` Dmitry Osipenko
2020-04-13 15:01 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 12/22] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 14/22] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 15/22] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 18/22] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-03-30 1:09 ` Dmitry Osipenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200330010904.27643-10-digetx@gmail.com \
--to=digetx-re5jqeeqqe8avxtiumwx3w@public.gmane.org \
--cc=a.swigon-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org \
--cc=devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
--cc=georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org \
--cc=jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org \
--cc=linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org \
--cc=thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.