From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> To: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>, Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>, Philipp Tomsich <philipp.tomsich-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org> Cc: patrick-Er2xLVyhcs+zQB+pC5nmwQ@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Tom Cubie <tom-jhlD/3HTYFgAvxtiuMwx3w@public.gmane.org>, Manivannan Sadhasivam <manivannan.sadhasivam-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org, Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>, sunil-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org, linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org Subject: [PATCH 8/8] rockchip: Enable PCIe/M.2 on rock960 board Date: Sat, 25 Apr 2020 16:33:54 +0530 [thread overview] Message-ID: <20200425110354.12381-9-jagan@amarulasolutions.com> (raw) In-Reply-To: <20200425110354.12381-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> Due to some on board limitation rock960 PCIe works only with 1.8V IO domain. So, this patch enables grf io_sel explicitly to make PCIe/M.2 to work. rock960 => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x0100 Bridge device 0x04 rock960 => nvme scan rock960 => nvme dev IDE device 0: Vendor: 0x144d Rev: 4L1QCXB7 Prod: S35FNX0J623292 Type: Hard Disk Capacity: 122104.3 MB = 119.2 GB (250069680 x 512) Cc: Tom Cubie <tom-jhlD/3HTYFgAvxtiuMwx3w@public.gmane.org> Cc: Manivannan Sadhasivam <manivannan.sadhasivam-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> --- board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 ++++++++++++++++++++ configs/rock960-rk3399_defconfig | 5 +++++ 2 files changed, 25 insertions(+) diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 68a127b9ac..98d62e89ca 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -2,3 +2,23 @@ /* * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> */ + +#include <common.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, BIT(0)); + + return 0; +} +#endif diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index c4e954731a..cb1ec3c26b 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" +CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y @@ -19,6 +20,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -36,10 +38,13 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y +CONFIG_NVME=y +CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Jagan Teki <jagan@amarulasolutions.com> To: u-boot@lists.denx.de Subject: [PATCH 8/8] rockchip: Enable PCIe/M.2 on rock960 board Date: Sat, 25 Apr 2020 16:33:54 +0530 [thread overview] Message-ID: <20200425110354.12381-9-jagan@amarulasolutions.com> (raw) In-Reply-To: <20200425110354.12381-1-jagan@amarulasolutions.com> Due to some on board limitation rock960 PCIe works only with 1.8V IO domain. So, this patch enables grf io_sel explicitly to make PCIe/M.2 to work. rock960 => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x0100 Bridge device 0x04 rock960 => nvme scan rock960 => nvme dev IDE device 0: Vendor: 0x144d Rev: 4L1QCXB7 Prod: S35FNX0J623292 Type: Hard Disk Capacity: 122104.3 MB = 119.2 GB (250069680 x 512) Cc: Tom Cubie <tom@radxa.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 ++++++++++++++++++++ configs/rock960-rk3399_defconfig | 5 +++++ 2 files changed, 25 insertions(+) diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 68a127b9ac..98d62e89ca 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -2,3 +2,23 @@ /* * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> */ + +#include <common.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, BIT(0)); + + return 0; +} +#endif diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index c4e954731a..cb1ec3c26b 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" +CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y @@ -19,6 +20,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -36,10 +38,13 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y +CONFIG_NVME=y +CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y -- 2.17.1
next prev parent reply other threads:[~2020-04-25 11:03 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-25 11:03 [PATCH 0/8] rockchip: Add PCIe host support Jagan Teki 2020-04-25 11:03 ` Jagan Teki [not found] ` <20200425110354.12381-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> 2020-04-25 11:03 ` [PATCH 1/8] iopoll: Add dealy to read poll Jagan Teki 2020-04-25 11:03 ` Jagan Teki 2020-04-25 11:03 ` [PATCH 2/8] iopoll: Add readl_poll_sleep_timeout Jagan Teki 2020-04-25 11:03 ` Jagan Teki 2020-04-25 11:03 ` [PATCH 3/8] clk: rk3399: Enable PCIE_PHY clock Jagan Teki 2020-04-25 11:03 ` Jagan Teki 2020-04-25 20:24 ` Mark Kettenis 2020-04-25 20:24 ` Mark Kettenis [not found] ` <016196395ae8077b-Sse5TxTiDWuxJFhkpKByzTXZidJgq2Oi@public.gmane.org> 2020-04-26 9:38 ` Jagan Teki 2020-04-26 9:38 ` Jagan Teki 2020-04-25 11:03 ` [PATCH 4/8] clk: rk3399: Disable " Jagan Teki 2020-04-25 11:03 ` Jagan Teki [not found] ` <20200425110354.12381-5-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> 2020-04-28 9:53 ` [PATCH 4/8] clk: rk3399: Disable PCIE_PHY clock【请注意,邮件由linux-rockchip-bounces+kever.yang=rock-chips.com@lists.infradead.org代发】 Kever Yang 2020-04-28 9:53 ` Kever Yang 2020-04-25 11:03 ` [PATCH 5/8] pci: Add Rockchip PCIe controller driver Jagan Teki 2020-04-25 11:03 ` Jagan Teki 2020-04-25 18:53 ` Mark Kettenis 2020-04-25 18:53 ` Mark Kettenis 2020-04-25 19:36 ` Jagan Teki 2020-04-25 19:36 ` Jagan Teki 2020-04-25 20:29 ` Mark Kettenis 2020-04-25 20:29 ` Mark Kettenis 2020-04-28 19:09 ` Jagan Teki 2020-04-28 19:09 ` Jagan Teki [not found] ` <CAMty3ZC+DiW2gGjN3rWcrwHPXZfxuGhjJN-1caUXW-Ry7VNR+A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2020-04-27 17:19 ` Robin Murphy 2020-04-27 17:19 ` Robin Murphy [not found] ` <20200425110354.12381-6-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> 2020-04-25 23:51 ` [PATCH 5/8] pci: Add Rockchip PCIe controller driver【请注意,邮件由linux-rockchip-bounces+shawn.lin=rock-chips.com@lists.infradead.org代发】 Shawn Lin 2020-04-25 23:51 ` Shawn Lin 2020-04-28 19:39 ` Jagan Teki 2020-04-28 19:39 ` Jagan Teki 2020-04-28 9:53 ` [PATCH 5/8] pci: Add Rockchip PCIe controller driver Kever Yang 2020-04-28 9:53 ` Kever Yang 2020-04-25 11:03 ` [PATCH 6/8] pci: Add Rockchip PCIe PHY " Jagan Teki 2020-04-25 11:03 ` Jagan Teki 2020-04-25 11:03 ` [PATCH 7/8] rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2 Jagan Teki 2020-04-25 11:03 ` Jagan Teki 2020-04-25 11:03 ` Jagan Teki [this message] 2020-04-25 11:03 ` [PATCH 8/8] rockchip: Enable PCIe/M.2 on rock960 board Jagan Teki
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