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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>, Tom Joseph <tjoseph@cadence.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <kishon@ti.com>
Subject: [PATCH v4 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path
Date: Wed, 6 May 2020 20:44:16 +0530	[thread overview]
Message-ID: <20200506151429.12255-2-kishon@ti.com> (raw)
In-Reply-To: <20200506151429.12255-1-kishon@ti.com>

commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core
library") while refactoring the Cadence PCIe driver to be used as
library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup()
and cdns_pcie_host_setup() but missed to remove the corresponding
pm_runtime_put_sync() in the error path. Fix it here.

Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/cadence/pcie-cadence-ep.c   | 9 ++-------
 drivers/pci/controller/cadence/pcie-cadence-host.c | 6 +-----
 2 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index 1c173dad67d1..1fdae37843ef 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -8,7 +8,6 @@
 #include <linux/of.h>
 #include <linux/pci-epc.h>
 #include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
 #include <linux/sizes.h>
 
 #include "pcie-cadence.h"
@@ -440,8 +439,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 	epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
 	if (IS_ERR(epc)) {
 		dev_err(dev, "failed to create epc device\n");
-		ret = PTR_ERR(epc);
-		goto err_init;
+		return PTR_ERR(epc);
 	}
 
 	epc_set_drvdata(epc, ep);
@@ -453,7 +451,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 			       resource_size(pcie->mem_res));
 	if (ret < 0) {
 		dev_err(dev, "failed to initialize the memory space\n");
-		goto err_init;
+		return ret;
 	}
 
 	ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
@@ -472,8 +470,5 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
  free_epc_mem:
 	pci_epc_mem_exit(epc);
 
- err_init:
-	pm_runtime_put_sync(dev);
-
 	return ret;
 }
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 31e67c9c88cf..465607202bb5 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -7,7 +7,6 @@
 #include <linux/of_address.h>
 #include <linux/of_pci.h>
 #include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
 
 #include "pcie-cadence.h"
 
@@ -259,7 +258,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 
 	ret = cdns_pcie_host_init(dev, &resources, rc);
 	if (ret)
-		goto err_init;
+		return ret;
 
 	list_splice_init(&resources, &bridge->windows);
 	bridge->dev.parent = dev;
@@ -277,8 +276,5 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
  err_host_probe:
 	pci_free_resource_list(&resources);
 
- err_init:
-	pm_runtime_put_sync(dev);
-
 	return ret;
 }
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>, Tom Joseph <tjoseph@cadence.com>
Cc: devicetree@vger.kernel.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	linux-kernel@vger.kernel.org, kishon@ti.com,
	linux-pci@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path
Date: Wed, 6 May 2020 20:44:16 +0530	[thread overview]
Message-ID: <20200506151429.12255-2-kishon@ti.com> (raw)
In-Reply-To: <20200506151429.12255-1-kishon@ti.com>

commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core
library") while refactoring the Cadence PCIe driver to be used as
library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup()
and cdns_pcie_host_setup() but missed to remove the corresponding
pm_runtime_put_sync() in the error path. Fix it here.

Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/cadence/pcie-cadence-ep.c   | 9 ++-------
 drivers/pci/controller/cadence/pcie-cadence-host.c | 6 +-----
 2 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index 1c173dad67d1..1fdae37843ef 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -8,7 +8,6 @@
 #include <linux/of.h>
 #include <linux/pci-epc.h>
 #include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
 #include <linux/sizes.h>
 
 #include "pcie-cadence.h"
@@ -440,8 +439,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 	epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
 	if (IS_ERR(epc)) {
 		dev_err(dev, "failed to create epc device\n");
-		ret = PTR_ERR(epc);
-		goto err_init;
+		return PTR_ERR(epc);
 	}
 
 	epc_set_drvdata(epc, ep);
@@ -453,7 +451,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 			       resource_size(pcie->mem_res));
 	if (ret < 0) {
 		dev_err(dev, "failed to initialize the memory space\n");
-		goto err_init;
+		return ret;
 	}
 
 	ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
@@ -472,8 +470,5 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
  free_epc_mem:
 	pci_epc_mem_exit(epc);
 
- err_init:
-	pm_runtime_put_sync(dev);
-
 	return ret;
 }
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 31e67c9c88cf..465607202bb5 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -7,7 +7,6 @@
 #include <linux/of_address.h>
 #include <linux/of_pci.h>
 #include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
 
 #include "pcie-cadence.h"
 
@@ -259,7 +258,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 
 	ret = cdns_pcie_host_init(dev, &resources, rc);
 	if (ret)
-		goto err_init;
+		return ret;
 
 	list_splice_init(&resources, &bridge->windows);
 	bridge->dev.parent = dev;
@@ -277,8 +276,5 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
  err_host_probe:
 	pci_free_resource_list(&resources);
 
- err_init:
-	pm_runtime_put_sync(dev);
-
 	return ret;
 }
-- 
2.17.1


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  reply	other threads:[~2020-05-06 15:14 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-06 15:14 [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-05-06 15:14 ` Kishon Vijay Abraham I
2020-05-06 15:14 ` Kishon Vijay Abraham I [this message]
2020-05-06 15:14   ` [PATCH v4 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-05-20 20:59   ` Rob Herring
2020-05-20 20:59     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:00   ` Rob Herring
2020-05-20 21:00     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 03/14] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:02   ` Rob Herring
2020-05-20 21:02     ` Rob Herring
2020-05-20 22:07   ` Rob Herring
2020-05-20 22:07     ` Rob Herring
2020-05-21 13:33     ` Kishon Vijay Abraham I
2020-05-21 13:33       ` Kishon Vijay Abraham I
2020-05-21 22:17       ` Rob Herring
2020-05-21 22:17         ` Rob Herring
2020-05-22  3:36         ` Kishon Vijay Abraham I
2020-05-22  3:36           ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 04/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:06   ` Rob Herring
2020-05-20 21:06     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 05/14] PCI: cadence: Add read/write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 06/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:34   ` Rob Herring
2020-05-20 21:34     ` Rob Herring
2020-05-21 11:34     ` Kishon Vijay Abraham I
2020-05-21 11:34       ` Kishon Vijay Abraham I
2020-05-22 16:45       ` Rob Herring
2020-05-22 16:45         ` Rob Herring
2020-05-23  1:24         ` Kishon Vijay Abraham I
2020-05-23  1:24           ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:36   ` Rob Herring
2020-05-20 21:36     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 22:12   ` Rob Herring
2020-05-20 22:12     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 22:12   ` Rob Herring
2020-05-20 22:12     ` Rob Herring
2020-05-18 11:14 ` [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-05-18 11:14   ` Kishon Vijay Abraham I

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