From: Vignesh Raghavendra <vigneshr@ti.com> To: Tudor Ambarus <tudor.ambarus@microchip.com>, Mark Brown <broonie@kernel.org> Cc: Vignesh Raghavendra <vigneshr@ti.com>, Boris Brezillon <bbrezillon@kernel.org>, Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <simon.k.r.goldschmidt@gmail.com>, <dinguyen@kernel.org>, <marex@denx.de> Subject: [PATCH 1/6] mtd: spi-nor: cadence-quadspi: Drop cdns,is-decoded-cs property Date: Sat, 9 May 2020 00:24:06 +0530 [thread overview] Message-ID: <20200508185411.487-2-vigneshr@ti.com> (raw) In-Reply-To: <20200508185411.487-1-vigneshr@ti.com> Cadence QSPI provides a way to automatically decode CS based on the offset accessed within memory map window. This feature cannot be supported in spi-mem framework as controller driver would not have access to flash geometry. Therefore drop this feature in preparation to moving to spi-mem. Note that, this feature never worked in the driver (Direct/Indirect mode accesses did not take into account size of flash on other CSs) and there are no users of this feature in kernel. Therefore dropping this should not cause a regression Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> --- .../mtd/spi-nor/controllers/cadence-quadspi.c | 59 +++---------------- 1 file changed, 9 insertions(+), 50 deletions(-) diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c index 494dcab4aaaa..fa54f85e16d7 100644 --- a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c @@ -77,11 +77,7 @@ struct cqspi_st { dma_addr_t mmap_phys_base; int current_cs; - int current_page_size; - int current_erase_size; - int current_addr_width; unsigned long master_ref_clk_hz; - bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; bool rclk_en; @@ -715,19 +711,15 @@ static void cqspi_chipselect(struct spi_nor *nor) unsigned int reg; reg = readl(reg_base + CQSPI_REG_CONFIG); - if (cqspi->is_decoded_cs) { - reg |= CQSPI_REG_CONFIG_DECODE_MASK; - } else { - reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; + reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; - /* Convert CS if without decoder. - * CS0 to 4b'1110 - * CS1 to 4b'1101 - * CS2 to 4b'1011 - * CS3 to 4b'0111 - */ - chip_select = 0xF & ~(1 << chip_select); - } + /* Convert CS if without decoder. + * CS0 to 4b'1110 + * CS1 to 4b'1101 + * CS2 to 4b'1011 + * CS3 to 4b'0111 + */ + chip_select = 0xF & ~(1 << chip_select); reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK << CQSPI_REG_CONFIG_CHIPSELECT_LSB); @@ -736,32 +728,6 @@ static void cqspi_chipselect(struct spi_nor *nor) writel(reg, reg_base + CQSPI_REG_CONFIG); } -static void cqspi_configure_cs_and_sizes(struct spi_nor *nor) -{ - struct cqspi_flash_pdata *f_pdata = nor->priv; - struct cqspi_st *cqspi = f_pdata->cqspi; - void __iomem *iobase = cqspi->iobase; - unsigned int reg; - - /* configure page size and block size. */ - reg = readl(iobase + CQSPI_REG_SIZE); - reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); - reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); - reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; - reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB); - reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB); - reg |= (nor->addr_width - 1); - writel(reg, iobase + CQSPI_REG_SIZE); - - /* configure the chip select */ - cqspi_chipselect(nor); - - /* Store the new configuration of the controller */ - cqspi->current_page_size = nor->page_size; - cqspi->current_erase_size = nor->mtd.erasesize; - cqspi->current_addr_width = nor->addr_width; -} - static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, const unsigned int ns_val) { @@ -867,18 +833,13 @@ static void cqspi_configure(struct spi_nor *nor) int switch_cs = (cqspi->current_cs != f_pdata->cs); int switch_ck = (cqspi->sclk != sclk); - if ((cqspi->current_page_size != nor->page_size) || - (cqspi->current_erase_size != nor->mtd.erasesize) || - (cqspi->current_addr_width != nor->addr_width)) - switch_cs = 1; - if (switch_cs || switch_ck) cqspi_controller_enable(cqspi, 0); /* Switch chip select. */ if (switch_cs) { cqspi->current_cs = f_pdata->cs; - cqspi_configure_cs_and_sizes(nor); + cqspi_chipselect(nor); } /* Setup baudrate divisor and delays */ @@ -1145,8 +1106,6 @@ static int cqspi_of_get_pdata(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct cqspi_st *cqspi = platform_get_drvdata(pdev); - cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); - if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { dev_err(&pdev->dev, "couldn't determine fifo-depth\n"); return -ENXIO; -- 2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Vignesh Raghavendra <vigneshr@ti.com> To: Tudor Ambarus <tudor.ambarus@microchip.com>, Mark Brown <broonie@kernel.org> Cc: marex@denx.de, Vignesh Raghavendra <vigneshr@ti.com>, Boris Brezillon <bbrezillon@kernel.org>, dinguyen@kernel.org, simon.k.r.goldschmidt@gmail.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>, linux-mtd@lists.infradead.org Subject: [PATCH 1/6] mtd: spi-nor: cadence-quadspi: Drop cdns, is-decoded-cs property Date: Sat, 9 May 2020 00:24:06 +0530 [thread overview] Message-ID: <20200508185411.487-2-vigneshr@ti.com> (raw) In-Reply-To: <20200508185411.487-1-vigneshr@ti.com> Cadence QSPI provides a way to automatically decode CS based on the offset accessed within memory map window. This feature cannot be supported in spi-mem framework as controller driver would not have access to flash geometry. Therefore drop this feature in preparation to moving to spi-mem. Note that, this feature never worked in the driver (Direct/Indirect mode accesses did not take into account size of flash on other CSs) and there are no users of this feature in kernel. Therefore dropping this should not cause a regression Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> --- .../mtd/spi-nor/controllers/cadence-quadspi.c | 59 +++---------------- 1 file changed, 9 insertions(+), 50 deletions(-) diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c index 494dcab4aaaa..fa54f85e16d7 100644 --- a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c @@ -77,11 +77,7 @@ struct cqspi_st { dma_addr_t mmap_phys_base; int current_cs; - int current_page_size; - int current_erase_size; - int current_addr_width; unsigned long master_ref_clk_hz; - bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; bool rclk_en; @@ -715,19 +711,15 @@ static void cqspi_chipselect(struct spi_nor *nor) unsigned int reg; reg = readl(reg_base + CQSPI_REG_CONFIG); - if (cqspi->is_decoded_cs) { - reg |= CQSPI_REG_CONFIG_DECODE_MASK; - } else { - reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; + reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; - /* Convert CS if without decoder. - * CS0 to 4b'1110 - * CS1 to 4b'1101 - * CS2 to 4b'1011 - * CS3 to 4b'0111 - */ - chip_select = 0xF & ~(1 << chip_select); - } + /* Convert CS if without decoder. + * CS0 to 4b'1110 + * CS1 to 4b'1101 + * CS2 to 4b'1011 + * CS3 to 4b'0111 + */ + chip_select = 0xF & ~(1 << chip_select); reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK << CQSPI_REG_CONFIG_CHIPSELECT_LSB); @@ -736,32 +728,6 @@ static void cqspi_chipselect(struct spi_nor *nor) writel(reg, reg_base + CQSPI_REG_CONFIG); } -static void cqspi_configure_cs_and_sizes(struct spi_nor *nor) -{ - struct cqspi_flash_pdata *f_pdata = nor->priv; - struct cqspi_st *cqspi = f_pdata->cqspi; - void __iomem *iobase = cqspi->iobase; - unsigned int reg; - - /* configure page size and block size. */ - reg = readl(iobase + CQSPI_REG_SIZE); - reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); - reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); - reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; - reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB); - reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB); - reg |= (nor->addr_width - 1); - writel(reg, iobase + CQSPI_REG_SIZE); - - /* configure the chip select */ - cqspi_chipselect(nor); - - /* Store the new configuration of the controller */ - cqspi->current_page_size = nor->page_size; - cqspi->current_erase_size = nor->mtd.erasesize; - cqspi->current_addr_width = nor->addr_width; -} - static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, const unsigned int ns_val) { @@ -867,18 +833,13 @@ static void cqspi_configure(struct spi_nor *nor) int switch_cs = (cqspi->current_cs != f_pdata->cs); int switch_ck = (cqspi->sclk != sclk); - if ((cqspi->current_page_size != nor->page_size) || - (cqspi->current_erase_size != nor->mtd.erasesize) || - (cqspi->current_addr_width != nor->addr_width)) - switch_cs = 1; - if (switch_cs || switch_ck) cqspi_controller_enable(cqspi, 0); /* Switch chip select. */ if (switch_cs) { cqspi->current_cs = f_pdata->cs; - cqspi_configure_cs_and_sizes(nor); + cqspi_chipselect(nor); } /* Setup baudrate divisor and delays */ @@ -1145,8 +1106,6 @@ static int cqspi_of_get_pdata(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct cqspi_st *cqspi = platform_get_drvdata(pdev); - cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); - if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { dev_err(&pdev->dev, "couldn't determine fifo-depth\n"); return -ENXIO; -- 2.26.2 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-05-08 18:54 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-08 18:54 [PATCH 0/6] mtd: spi-nor: Move cadence-qaudspi to spi-mem framework Vignesh Raghavendra 2020-05-08 18:54 ` Vignesh Raghavendra 2020-05-08 18:54 ` Vignesh Raghavendra [this message] 2020-05-08 18:54 ` [PATCH 1/6] mtd: spi-nor: cadence-quadspi: Drop cdns, is-decoded-cs property Vignesh Raghavendra 2020-05-26 9:31 ` [PATCH 1/6] mtd: spi-nor: cadence-quadspi: Drop cdns,is-decoded-cs property Vignesh Raghavendra 2020-05-26 9:31 ` Vignesh Raghavendra 2020-05-08 18:54 ` [PATCH 2/6] mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC mode Vignesh Raghavendra 2020-05-08 18:54 ` Vignesh Raghavendra 2020-05-28 18:37 ` Tudor.Ambarus 2020-05-28 18:37 ` Tudor.Ambarus 2020-05-08 18:54 ` [PATCH 3/6] mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on failure Vignesh Raghavendra 2020-05-08 18:54 ` Vignesh Raghavendra 2020-05-08 18:54 ` [PATCH 4/6] mtd: spi-nor: cadence-quadspi: Fix error path on failure to acquire reset lines Vignesh Raghavendra 2020-05-08 18:54 ` Vignesh Raghavendra 2020-05-08 18:54 ` [PATCH 5/6] mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework Vignesh Raghavendra 2020-05-08 18:54 ` Vignesh Raghavendra 2020-05-08 18:54 ` [PATCH 6/6] spi: Move cadence-quadspi driver to drivers/spi/ Vignesh Raghavendra 2020-05-08 18:54 ` Vignesh Raghavendra 2020-05-11 10:20 ` [PATCH 0/6] mtd: spi-nor: Move cadence-qaudspi to spi-mem framework Ramuthevar, Vadivel MuruganX 2020-05-11 10:20 ` Ramuthevar, Vadivel MuruganX
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