From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 00/28] Introduce DG1
Date: Wed, 1 Jul 2020 16:53:11 -0700 [thread overview]
Message-ID: <20200701235339.32608-1-lucas.demarchi@intel.com> (raw)
v3:
- Make sure we don't bind the driver to the device while the driver is
not complete. This should unblock us to have these basic patches
merged so the next parts can be developed/refactored/implemented,
particularly related to lmem.
When we have these patches applied and lmem part working for at least
a display-only driver we can make it bind again. This guarantees we
don't regress.
- Remove most of the RKL patches. The only one I'm still carrying is the
one for WAs as they are very similar to the ones for DG1.
Particularly the patch for PLL on RKL was making CI for this series to
fail, so untangle both and let them both continue the review process
in parallel.
v2:
- Remove some wrong/unneeded patches
- Collect R-b
- Rebase
As in previous version, the RKL patches are here only for completeness
and avoid future conflicts, not to be reviewed/applied.
Original cover:
DG1 is a gen12 dgfx platform. This is the first batch of patches to
support it. It also depends on some in-flight patches adding RKL. In
order for this series to be compiled, I'm including them here.
While converting some of these patches to the current
intel_uncore/intel_de APIs I thought it could be useful to return the
previous value. The patch for that is included here, but I ended up
not using and it can be dropped if there is no interest.
Abdiel Janulgue (2):
drm/i915/dg1: add initial DG-1 definitions
drm/i915/dg1: Add DG1 PCI IDs
Aditya Swarup (4):
drm/i915/dg1: Add DPLL macros for DG1
drm/i915/dg1: Add and setup DPLLs for DG1
drm/i915/dg1: Enable DPLL for DG1
drm/i915/dg1: Enable first 2 ports for DG1
Anshuman Gupta (1):
drm/i915/dg1: DG1 does not support DC6
Anusha Srivatsa (1):
drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
Clinton A Taylor (1):
drm/i915/dg1: invert HPD pins
Lucas De Marchi (7):
drm/i915/dg1: add support for the master unit interrupt
drm/i915/dg1: Add fake PCH
drm/i915/dg1: Define MOCS table for DG1
drm/i915/dg1: add hpd interrupt handling
drm/i915/dg1: gmbus pin mapping
drm/i915/dg1: map/unmap pll clocks
drm/i915/dg1: enable PORT C/D aka D/E
Matt Atwood (1):
drm/i915/dg1: Load DMC
Matt Roper (7):
drm/i915/dg1: Initialize RAWCLK properly
drm/i915/dg1: Wait for pcode/uncore handshake at startup
drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
drm/i915/dg1: Update comp master/slave relationships for PHYs
drm/i915/dg1: Update voltage swing tables for DP
drm/i915/dg1: provide port/phy mapping for vbt
drm/i915/rkl: Add initial workarounds
Stuart Summers (2):
drm/i915: Add has_master_unit_irq flag
drm/i915/dg1: Add initial DG1 workarounds
Uma Shankar (1):
drm/i915/dg1: Add DG1 power wells
Venkata Sandeep Dhanalakota (1):
drm/i915/dg1: Increase mmio size to 4MB
drivers/gpu/drm/i915/display/intel_bios.c | 12 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 7 +-
drivers/gpu/drm/i915/display/intel_csr.c | 19 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 126 ++++++++++-
drivers/gpu/drm/i915/display/intel_display.c | 50 ++++-
.../drm/i915/display/intel_display_power.c | 211 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 71 ++++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 ++
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 3 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 159 ++++++++++---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/i915_irq.c | 120 +++++++++-
drivers/gpu/drm/i915/i915_pci.c | 14 ++
drivers/gpu/drm/i915/i915_reg.h | 65 +++++-
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 2 +
drivers/gpu/drm/i915/intel_pch.c | 6 +
drivers/gpu/drm/i915/intel_pch.h | 4 +
drivers/gpu/drm/i915/intel_pm.c | 17 +-
drivers/gpu/drm/i915/intel_sideband.c | 15 ++
drivers/gpu/drm/i915/intel_sideband.h | 2 +
drivers/gpu/drm/i915/intel_uncore.c | 4 +
include/drm/i915_pciids.h | 4 +
30 files changed, 930 insertions(+), 99 deletions(-)
--
2.26.2
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next reply other threads:[~2020-07-01 23:54 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 23:53 Lucas De Marchi [this message]
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 01/28] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 02/28] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-07-02 6:00 ` kernel test robot
2020-07-02 6:00 ` kernel test robot
2020-07-09 20:01 ` Lucas De Marchi
2020-07-09 20:56 ` Lucas De Marchi
2020-07-02 12:37 ` kernel test robot
2020-07-02 12:37 ` kernel test robot
2020-07-08 17:08 ` Daniel Vetter
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 04/28] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 05/28] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-07-08 7:28 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 07/28] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 08/28] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 09/28] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 10/28] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 11/28] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 12/28] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 13/28] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 14/28] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 15/28] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 16/28] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 17/28] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 18/28] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-07-08 7:17 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-07-08 7:51 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-07-08 10:23 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 22/28] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 23/28] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 24/28] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 25/28] drm/i915/dg1: Load DMC Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 26/28] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 27/28] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 28/28] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-07-02 0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev3) Patchwork
2020-07-02 0:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-02 0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02 4:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-02 7:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev4) Patchwork
2020-07-02 7:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-02 8:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02 11:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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