From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 16/28] drm/i915/dg1: invert HPD pins
Date: Wed, 1 Jul 2020 16:53:27 -0700 [thread overview]
Message-ID: <20200701235339.32608-17-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20200701235339.32608-1-lucas.demarchi@intel.com>
From: Clinton A Taylor <clinton.a.taylor@intel.com>
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e8bdc52c94bb..6225390edbb4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3181,6 +3181,10 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
+ intel_de_rmw(dev_priv, SOUTH_CHICKEN1, 0,
+ INVERT_DDIA_HPD | INVERT_DDIB_HPD |
+ INVERT_DDIC_HPD | INVERT_DDID_HPD);
+
icp_hpd_irq_setup(dev_priv,
SDE_DDI_MASK_DG1, 0,
DG1_DDI_HPD_ENABLE_MASK, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6a853088a6e2..6b5dee1a82e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8687,6 +8687,10 @@ enum {
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDID_HPD (1 << 18)
+#define INVERT_DDIC_HPD (1 << 17)
+#define INVERT_DDIB_HPD (1 << 16)
+#define INVERT_DDIA_HPD (1 << 15)
#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
#define FDI_BC_BIFURCATION_SELECT (1 << 12)
--
2.26.2
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next prev parent reply other threads:[~2020-07-01 23:55 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 01/28] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 02/28] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-07-02 6:00 ` kernel test robot
2020-07-02 6:00 ` kernel test robot
2020-07-09 20:01 ` Lucas De Marchi
2020-07-09 20:56 ` Lucas De Marchi
2020-07-02 12:37 ` kernel test robot
2020-07-02 12:37 ` kernel test robot
2020-07-08 17:08 ` Daniel Vetter
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 04/28] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 05/28] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-07-08 7:28 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 07/28] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 08/28] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 09/28] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 10/28] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 11/28] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 12/28] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 13/28] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 14/28] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 15/28] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-07-01 23:53 ` Lucas De Marchi [this message]
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 17/28] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 18/28] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-07-08 7:17 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-07-08 7:51 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-07-08 10:23 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 22/28] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 23/28] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 24/28] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 25/28] drm/i915/dg1: Load DMC Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 26/28] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 27/28] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 28/28] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-07-02 0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev3) Patchwork
2020-07-02 0:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-02 0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02 4:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-02 7:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev4) Patchwork
2020-07-02 7:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-02 8:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02 11:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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