From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PULL v2 28/64] target/riscv: vector single-width averaging add and subtract
Date: Thu, 2 Jul 2020 09:23:18 -0700 [thread overview]
Message-ID: <20200702162354.928528-29-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200702162354.928528-1-alistair.francis@wdc.com>
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-26-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 17 ++++
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c | 100 ++++++++++++++++++++++++
4 files changed, 129 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 85bd4b91bc..db9e2024ae 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -725,3 +725,20 @@ DEF_HELPER_6(vssub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 70df42de9a..57228242aa 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -419,6 +419,11 @@ vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
+vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm
+vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm
+vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm
+vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm
+vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index a2ab14ade0..354a802518 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1747,3 +1747,10 @@ GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
GEN_OPIVX_TRANS(vssub_vx, opivx_check)
GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
+
+/* Vector Single-Width Averaging Add and Subtract */
+GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
+GEN_OPIVV_TRANS(vasub_vv, opivv_check)
+GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vasub_vx, opivx_check)
+GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1277aa1c10..0b2119b6cc 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2497,3 +2497,103 @@ GEN_VEXT_VX_RM(vssub_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vssub_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vssub_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vssub_vx_d, 8, 8, clearq)
+
+/* Vector Single-Width Averaging Add and Subtract */
+static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
+{
+ uint8_t d = extract64(v, shift, 1);
+ uint8_t d1;
+ uint64_t D1, D2;
+
+ if (shift == 0 || shift > 64) {
+ return 0;
+ }
+
+ d1 = extract64(v, shift - 1, 1);
+ D1 = extract64(v, 0, shift);
+ if (vxrm == 0) { /* round-to-nearest-up (add +0.5 LSB) */
+ return d1;
+ } else if (vxrm == 1) { /* round-to-nearest-even */
+ if (shift > 1) {
+ D2 = extract64(v, 0, shift - 1);
+ return d1 & ((D2 != 0) | d);
+ } else {
+ return d1 & d;
+ }
+ } else if (vxrm == 3) { /* round-to-odd (OR bits into LSB, aka "jam") */
+ return !d & (D1 != 0);
+ }
+ return 0; /* round-down (truncate) */
+}
+
+static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+{
+ int64_t res = (int64_t)a + b;
+ uint8_t round = get_round(vxrm, res, 1);
+
+ return (res >> 1) + round;
+}
+
+static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+{
+ int64_t res = a + b;
+ uint8_t round = get_round(vxrm, res, 1);
+ int64_t over = (res ^ a) & (res ^ b) & INT64_MIN;
+
+ /* With signed overflow, bit 64 is inverse of bit 63. */
+ return ((res >> 1) ^ over) + round;
+}
+
+RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
+RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
+RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
+RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
+GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8, clearq)
+
+RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
+RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
+RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
+RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
+GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl)
+GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq)
+
+static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+{
+ int64_t res = (int64_t)a - b;
+ uint8_t round = get_round(vxrm, res, 1);
+
+ return (res >> 1) + round;
+}
+
+static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+{
+ int64_t res = (int64_t)a - b;
+ uint8_t round = get_round(vxrm, res, 1);
+ int64_t over = (res ^ a) & (a ^ b) & INT64_MIN;
+
+ /* With signed overflow, bit 64 is inverse of bit 63. */
+ return ((res >> 1) ^ over) + round;
+}
+
+RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
+RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
+RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
+RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
+GEN_VEXT_VV_RM(vasub_vv_b, 1, 1, clearb)
+GEN_VEXT_VV_RM(vasub_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_RM(vasub_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_RM(vasub_vv_d, 8, 8, clearq)
+
+RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
+RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
+RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
+RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
+GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb)
+GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
+GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
+GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)
--
2.27.0
next prev parent reply other threads:[~2020-07-02 16:44 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 16:22 [PULL v2 00/64] riscv-to-apply queue Alistair Francis
2020-07-02 16:22 ` [PULL v2 01/64] riscv: plic: Honour source priorities Alistair Francis
2020-07-02 16:22 ` [PULL v2 02/64] riscv: plic: Add a couple of mising sifive_plic_update calls Alistair Francis
2020-07-02 16:22 ` [PULL v2 03/64] hw/riscv: Allow 64 bit access to SiFive CLINT Alistair Francis
2020-07-02 16:22 ` [PULL v2 04/64] target/riscv: add vector extension field in CPURISCVState Alistair Francis
2020-07-02 16:22 ` [PULL v2 05/64] target/riscv: implementation-defined constant parameters Alistair Francis
2020-07-02 16:22 ` [PULL v2 06/64] target/riscv: support vector extension csr Alistair Francis
2020-07-02 16:22 ` [PULL v2 07/64] target/riscv: add vector configure instruction Alistair Francis
2020-07-02 16:22 ` [PULL v2 08/64] target/riscv: add an internals.h header Alistair Francis
2020-07-02 16:22 ` [PULL v2 09/64] target/riscv: add vector stride load and store instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 10/64] target/riscv: add vector index " Alistair Francis
2020-07-02 16:23 ` [PULL v2 11/64] target/riscv: add fault-only-first unit stride load Alistair Francis
2020-07-02 16:23 ` [PULL v2 12/64] target/riscv: add vector amo operations Alistair Francis
2020-07-05 18:20 ` Peter Maydell
2020-07-06 20:48 ` Richard Henderson
2020-07-07 14:26 ` LIU Zhiwei
2020-07-07 14:33 ` Richard Henderson
2020-07-06 23:36 ` Alistair Francis
2020-07-07 2:35 ` LIU Zhiwei
2020-07-02 16:23 ` [PULL v2 13/64] target/riscv: vector single-width integer add and subtract Alistair Francis
2020-07-02 16:23 ` [PULL v2 14/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 15/64] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 16/64] target/riscv: vector bitwise logical instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 17/64] target/riscv: vector single-width bit shift instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 18/64] target/riscv: vector narrowing integer right " Alistair Francis
2020-07-02 16:23 ` [PULL v2 19/64] target/riscv: vector integer comparison instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 20/64] target/riscv: vector integer min/max instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 21/64] target/riscv: vector single-width integer multiply instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 22/64] target/riscv: vector integer divide instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 23/64] target/riscv: vector widening integer multiply instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 24/64] target/riscv: vector single-width integer multiply-add instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 25/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 26/64] target/riscv: vector integer merge and move instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 27/64] target/riscv: vector single-width saturating add and subtract Alistair Francis
2020-07-02 16:23 ` Alistair Francis [this message]
2020-07-02 16:23 ` [PULL v2 29/64] target/riscv: vector single-width fractional multiply with rounding and saturation Alistair Francis
2020-07-02 16:23 ` [PULL v2 30/64] target/riscv: vector widening saturating scaled multiply-add Alistair Francis
2020-07-02 16:23 ` [PULL v2 31/64] target/riscv: vector single-width scaling shift instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 32/64] target/riscv: vector narrowing fixed-point clip instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 33/64] target/riscv: vector single-width floating-point add/subtract instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 34/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 35/64] target/riscv: vector single-width floating-point multiply/divide instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 36/64] target/riscv: vector widening floating-point multiply Alistair Francis
2020-07-02 16:23 ` [PULL v2 37/64] target/riscv: vector single-width floating-point fused multiply-add instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 38/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 39/64] target/riscv: vector floating-point square-root instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 40/64] target/riscv: vector floating-point min/max instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 41/64] target/riscv: vector floating-point sign-injection instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 42/64] target/riscv: vector floating-point compare instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 43/64] target/riscv: vector floating-point classify instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 44/64] target/riscv: vector floating-point merge instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 45/64] target/riscv: vector floating-point/integer type-convert instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 46/64] target/riscv: widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 47/64] target/riscv: narrowing " Alistair Francis
2020-07-02 16:23 ` [PULL v2 48/64] target/riscv: vector single-width integer reduction instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 49/64] target/riscv: vector wideing " Alistair Francis
2020-07-02 16:23 ` [PULL v2 50/64] target/riscv: vector single-width floating-point " Alistair Francis
2020-07-02 16:23 ` [PULL v2 51/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 52/64] target/riscv: vector mask-register logical instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 53/64] target/riscv: vector mask population count vmpopc Alistair Francis
2020-07-02 16:23 ` [PULL v2 54/64] target/riscv: vmfirst find-first-set mask bit Alistair Francis
2020-07-02 16:23 ` [PULL v2 55/64] target/riscv: set-X-first " Alistair Francis
2020-07-02 16:23 ` [PULL v2 56/64] target/riscv: vector iota instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 57/64] target/riscv: vector element index instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 58/64] target/riscv: integer extract instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 59/64] target/riscv: integer scalar move instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 60/64] target/riscv: floating-point scalar move instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 61/64] target/riscv: vector slide instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 62/64] target/riscv: vector register gather instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 63/64] target/riscv: vector compress instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 64/64] target/riscv: configure and turn on vector extension from command line Alistair Francis
2020-07-02 17:27 ` [PULL v2 00/64] riscv-to-apply queue no-reply
2020-07-03 16:55 ` Peter Maydell
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