From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries
Date: Mon, 13 Jul 2020 17:32:41 -0700 [thread overview]
Message-ID: <20200714003254.4044149-3-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200714003254.4044149-1-alistair.francis@wdc.com>
From: Bin Meng <bin.meng@windriver.com>
Adjust the PCIe memory maps to follow the order.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1593746511-19517-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f7630c8a89..18283e262e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -60,14 +60,14 @@ static const struct MemmapEntry {
[VIRT_TEST] = { 0x100000, 0x1000 },
[VIRT_RTC] = { 0x101000, 0x1000 },
[VIRT_CLINT] = { 0x2000000, 0x10000 },
+ [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
[VIRT_PLIC] = { 0xc000000, 0x4000000 },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
- [VIRT_DRAM] = { 0x80000000, 0x0 },
- [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
- [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
+ [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
+ [VIRT_DRAM] = { 0x80000000, 0x0 },
};
#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
--
2.27.0
next prev parent reply other threads:[~2020-07-14 0:43 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
2020-07-14 0:32 ` [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware Alistair Francis
2020-07-14 0:32 ` Alistair Francis [this message]
2020-07-14 0:32 ` [PULL 03/15] riscv: Unify Qemu's reset vector code path Alistair Francis
2020-07-14 0:32 ` [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM Alistair Francis
2021-07-13 10:43 ` Peter Maydell
2021-07-14 6:35 ` Alistair Francis
2020-07-14 0:32 ` [PULL 05/15] riscv: Add opensbi firmware dynamic support Alistair Francis
2020-07-14 0:32 ` [PULL 06/15] RISC-V: Support 64 bit start address Alistair Francis
2020-07-14 0:32 ` [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000 Alistair Francis
2020-07-14 0:32 ` [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion Alistair Francis
2020-07-14 0:32 ` [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Alistair Francis
2020-07-14 0:32 ` [PULL 10/15] target/riscv: fix return value of do_opivx_widen() Alistair Francis
2020-07-14 0:32 ` [PULL 11/15] target/riscv: fix vill bit index in vtype register Alistair Francis
2020-07-14 0:32 ` [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model Alistair Francis
2020-07-14 0:32 ` [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API Alistair Francis
2020-07-14 0:32 ` [PULL 14/15] tcg/riscv: Remove superfluous breaks Alistair Francis
2020-07-14 0:32 ` [PULL 15/15] target/riscv: Fix pmp NA4 implementation Alistair Francis
2020-07-14 0:37 ` [PULL 00/15] riscv-to-apply queue Alistair Francis
2020-07-14 18:39 ` Peter Maydell
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