From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Jingoo Han <jingoohan1@gmail.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Fabio Estevam <festevam@gmail.com>,
Jesper Nilsson <jesper.nilsson@axis.com>,
Jonathan Chocron <jonnyc@amazon.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Kevin Hilman <khilman@baylibre.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Kukjin Kim <kgene@kernel.org>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org,
linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
linux-tegra@vger.kernel.org, Lucas Stach <l.stach@pengutronix.de>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Murali Karicheri <m-karicheri2@ti.com>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Pratyush Anand <pratyush.anand@gmail.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Thierry Reding <thierry.reding@gmail.com>,
Xiaowei Song <songxiaowei@hisilicon.com>,
Yue Wang <yue.wang@Amlogic.com>
Subject: [RFC 27/27] PCI: dwc/tegra: Use common Designware port logic register definitions
Date: Mon, 3 Aug 2020 15:01:16 -0600 [thread overview]
Message-ID: <20200803210116.3132633-28-robh@kernel.org> (raw)
In-Reply-To: <20200803210116.3132633-1-robh@kernel.org>
The Tegra driver has its own defines for common Designware Port Logic
registers. Convert it to use the standard register definitions.
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-pci@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-designware.h | 6 +++
drivers/pci/controller/dwc/pcie-tegra194.c | 56 ++++++++------------
2 files changed, 28 insertions(+), 34 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index b18a9a5f48d2..3bd322db69a6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -32,7 +32,13 @@
/* Synopsys-specific PCIe configuration registers */
#define PCIE_PORT_AFR 0x70C
#define PORT_AFR_N_FTS_MASK GENMASK(15, 8)
+#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n)
#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)
+#define PORT_AFR_ENTER_ASPM BIT(30)
+#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24
+#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
+#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27
+#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_DLL_LINK_EN BIT(5)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index c567c9c09ff6..ad295c854853 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -183,19 +183,7 @@
#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
#define EVENT_COUNTER_GROUP_5 0x5
-#define PORT_LOGIC_ACK_F_ASPM_CTRL 0x70C
-#define ENTER_ASPM BIT(30)
-#define L0S_ENTRANCE_LAT_SHIFT 24
-#define L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
-#define L1_ENTRANCE_LAT_SHIFT 27
-#define L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
-#define N_FTS_SHIFT 8
-#define N_FTS_MASK GENMASK(7, 0)
#define N_FTS_VAL 52
-
-#define PORT_LOGIC_GEN2_CTRL 0x80C
-#define PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE BIT(17)
-#define FTS_MASK GENMASK(7, 0)
#define FTS_VAL 52
#define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828
@@ -401,9 +389,9 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
}
}
@@ -694,11 +682,11 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
/* Program L0s and L1 entrance latencies */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~L0S_ENTRANCE_LAT_MASK;
- val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT);
- val |= ENTER_ASPM;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
+ val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
+ val |= PORT_AFR_ENTER_ASPM;
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
}
static int init_debugfs(struct tegra_pcie_dw *pcie)
@@ -895,15 +883,15 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
/* Configure FTS */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~(N_FTS_MASK << N_FTS_SHIFT);
- val |= N_FTS_VAL << N_FTS_SHIFT;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_N_FTS_MASK;
+ val |= PORT_AFR_N_FTS(N_FTS_VAL);
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val &= ~FTS_MASK;
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_N_FTS_MASK;
val |= FTS_VAL;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
/* Enable as 0xFFFF0001 response for CRS */
val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
@@ -1820,15 +1808,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
/* Configure N_FTS & FTS */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~(N_FTS_MASK << N_FTS_SHIFT);
- val |= N_FTS_VAL << N_FTS_SHIFT;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_N_FTS_MASK;
+ val |= PORT_AFR_N_FTS(FTS_VAL);
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val &= ~FTS_MASK;
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_N_FTS_MASK;
val |= FTS_VAL;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
/* Configure Max Speed from DT */
if (pcie->max_speed && pcie->max_speed != -EINVAL) {
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Jingoo Han <jingoohan1@gmail.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
linux-pci@vger.kernel.org,
Binghui Wang <wangbinghui@hisilicon.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Thierry Reding <thierry.reding@gmail.com>,
linux-arm-kernel@axis.com, Jonathan Chocron <jonnyc@amazon.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Fabio Estevam <festevam@gmail.com>,
Jesper Nilsson <jesper.nilsson@axis.com>,
linux-samsung-soc@vger.kernel.org,
Kevin Hilman <khilman@baylibre.com>,
Pratyush Anand <pratyush.anand@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Murali Karicheri <m-karicheri2@ti.com>,
NXP Linux Team <linux-imx@nxp.com>,
Xiaowei Song <songxiaowei@hisilicon.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
linux-arm-msm@vger.kernel.org,
Sascha Hauer <s.hauer@pengutronix.de>,
Yue Wang <yue.wang@Amlogic.com>,
linux-tegra@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Kukjin Kim <kgene@kernel.org>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
Lucas Stach <l.stach@pengutronix.de>
Subject: [RFC 27/27] PCI: dwc/tegra: Use common Designware port logic register definitions
Date: Mon, 3 Aug 2020 15:01:16 -0600 [thread overview]
Message-ID: <20200803210116.3132633-28-robh@kernel.org> (raw)
In-Reply-To: <20200803210116.3132633-1-robh@kernel.org>
The Tegra driver has its own defines for common Designware Port Logic
registers. Convert it to use the standard register definitions.
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-pci@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-designware.h | 6 +++
drivers/pci/controller/dwc/pcie-tegra194.c | 56 ++++++++------------
2 files changed, 28 insertions(+), 34 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index b18a9a5f48d2..3bd322db69a6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -32,7 +32,13 @@
/* Synopsys-specific PCIe configuration registers */
#define PCIE_PORT_AFR 0x70C
#define PORT_AFR_N_FTS_MASK GENMASK(15, 8)
+#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n)
#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)
+#define PORT_AFR_ENTER_ASPM BIT(30)
+#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24
+#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
+#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27
+#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_DLL_LINK_EN BIT(5)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index c567c9c09ff6..ad295c854853 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -183,19 +183,7 @@
#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
#define EVENT_COUNTER_GROUP_5 0x5
-#define PORT_LOGIC_ACK_F_ASPM_CTRL 0x70C
-#define ENTER_ASPM BIT(30)
-#define L0S_ENTRANCE_LAT_SHIFT 24
-#define L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
-#define L1_ENTRANCE_LAT_SHIFT 27
-#define L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
-#define N_FTS_SHIFT 8
-#define N_FTS_MASK GENMASK(7, 0)
#define N_FTS_VAL 52
-
-#define PORT_LOGIC_GEN2_CTRL 0x80C
-#define PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE BIT(17)
-#define FTS_MASK GENMASK(7, 0)
#define FTS_VAL 52
#define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828
@@ -401,9 +389,9 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
}
}
@@ -694,11 +682,11 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
/* Program L0s and L1 entrance latencies */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~L0S_ENTRANCE_LAT_MASK;
- val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT);
- val |= ENTER_ASPM;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
+ val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
+ val |= PORT_AFR_ENTER_ASPM;
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
}
static int init_debugfs(struct tegra_pcie_dw *pcie)
@@ -895,15 +883,15 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
/* Configure FTS */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~(N_FTS_MASK << N_FTS_SHIFT);
- val |= N_FTS_VAL << N_FTS_SHIFT;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_N_FTS_MASK;
+ val |= PORT_AFR_N_FTS(N_FTS_VAL);
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val &= ~FTS_MASK;
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_N_FTS_MASK;
val |= FTS_VAL;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
/* Enable as 0xFFFF0001 response for CRS */
val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
@@ -1820,15 +1808,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
/* Configure N_FTS & FTS */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~(N_FTS_MASK << N_FTS_SHIFT);
- val |= N_FTS_VAL << N_FTS_SHIFT;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_N_FTS_MASK;
+ val |= PORT_AFR_N_FTS(FTS_VAL);
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val &= ~FTS_MASK;
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_N_FTS_MASK;
val |= FTS_VAL;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
/* Configure Max Speed from DT */
if (pcie->max_speed && pcie->max_speed != -EINVAL) {
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Jingoo Han <jingoohan1@gmail.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
linux-pci@vger.kernel.org,
Binghui Wang <wangbinghui@hisilicon.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Thierry Reding <thierry.reding@gmail.com>,
linux-arm-kernel@axis.com, Jonathan Chocron <jonnyc@amazon.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Fabio Estevam <festevam@gmail.com>,
Jesper Nilsson <jesper.nilsson@axis.com>,
linux-samsung-soc@vger.kernel.org,
Kevin Hilman <khilman@baylibre.com>,
Pratyush Anand <pratyush.anand@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Murali Karicheri <m-karicheri2@ti.com>,
NXP Linux Team <linux-imx@nxp.com>,
Xiaowei Song <songxiaowei@hisilicon.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
linux-arm-msm@vger.kernel.org,
Sascha Hauer <s.hauer@pengutronix.de>,
Yue Wang <yue.wang@Amlogic.com>,
linux-tegra@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Kukjin Kim <kgene@kernel.org>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
Lucas Stach <l.stach@pengutronix.de>
Subject: [RFC 27/27] PCI: dwc/tegra: Use common Designware port logic register definitions
Date: Mon, 3 Aug 2020 15:01:16 -0600 [thread overview]
Message-ID: <20200803210116.3132633-28-robh@kernel.org> (raw)
In-Reply-To: <20200803210116.3132633-1-robh@kernel.org>
The Tegra driver has its own defines for common Designware Port Logic
registers. Convert it to use the standard register definitions.
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-pci@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-designware.h | 6 +++
drivers/pci/controller/dwc/pcie-tegra194.c | 56 ++++++++------------
2 files changed, 28 insertions(+), 34 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index b18a9a5f48d2..3bd322db69a6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -32,7 +32,13 @@
/* Synopsys-specific PCIe configuration registers */
#define PCIE_PORT_AFR 0x70C
#define PORT_AFR_N_FTS_MASK GENMASK(15, 8)
+#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n)
#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)
+#define PORT_AFR_ENTER_ASPM BIT(30)
+#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24
+#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
+#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27
+#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_DLL_LINK_EN BIT(5)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index c567c9c09ff6..ad295c854853 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -183,19 +183,7 @@
#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
#define EVENT_COUNTER_GROUP_5 0x5
-#define PORT_LOGIC_ACK_F_ASPM_CTRL 0x70C
-#define ENTER_ASPM BIT(30)
-#define L0S_ENTRANCE_LAT_SHIFT 24
-#define L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
-#define L1_ENTRANCE_LAT_SHIFT 27
-#define L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
-#define N_FTS_SHIFT 8
-#define N_FTS_MASK GENMASK(7, 0)
#define N_FTS_VAL 52
-
-#define PORT_LOGIC_GEN2_CTRL 0x80C
-#define PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE BIT(17)
-#define FTS_MASK GENMASK(7, 0)
#define FTS_VAL 52
#define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828
@@ -401,9 +389,9 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
}
}
@@ -694,11 +682,11 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
/* Program L0s and L1 entrance latencies */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~L0S_ENTRANCE_LAT_MASK;
- val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT);
- val |= ENTER_ASPM;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
+ val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
+ val |= PORT_AFR_ENTER_ASPM;
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
}
static int init_debugfs(struct tegra_pcie_dw *pcie)
@@ -895,15 +883,15 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
/* Configure FTS */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~(N_FTS_MASK << N_FTS_SHIFT);
- val |= N_FTS_VAL << N_FTS_SHIFT;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_N_FTS_MASK;
+ val |= PORT_AFR_N_FTS(N_FTS_VAL);
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val &= ~FTS_MASK;
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_N_FTS_MASK;
val |= FTS_VAL;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
/* Enable as 0xFFFF0001 response for CRS */
val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
@@ -1820,15 +1808,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
/* Configure N_FTS & FTS */
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
- val &= ~(N_FTS_MASK << N_FTS_SHIFT);
- val |= N_FTS_VAL << N_FTS_SHIFT;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+ val &= ~PORT_AFR_N_FTS_MASK;
+ val |= PORT_AFR_N_FTS(FTS_VAL);
+ dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
- val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
- val &= ~FTS_MASK;
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_N_FTS_MASK;
val |= FTS_VAL;
- dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
/* Configure Max Speed from DT */
if (pcie->max_speed && pcie->max_speed != -EINVAL) {
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2020-08-03 21:02 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-03 21:00 [RFC 00/27] PCI: dwc: Driver clean-ups Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 01/27] PCI: Allow root and child buses to have different pci_ops Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 02/27] PCI: dwc: Use DBI accessors instead of own config accessors Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 03/27] PCI: dwc: Allow overriding bridge pci_ops Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 04/27] PCI: dwc: Add a default pci_ops.map_bus for root port Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 05/27] PCI: dwc: al: Use pci_ops for child config space accessors Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 06/27] PCI: dwc: keystone: Use pci_ops for " Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 07/27] PCI: dwc: tegra: Use pci_ops for root " Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 08/27] PCI: dwc: meson: " Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 09/27] PCI: dwc: kirin: " Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` [RFC 10/27] PCI: dwc: exynos: " Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:00 ` Rob Herring
2020-08-03 21:01 ` [RFC 11/27] PCI: dwc: histb: " Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 12/27] PCI: dwc: Remove dwc specific config accessor ops Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 13/27] PCI: dwc: Use generic config accessors Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 14/27] PCI: Also call .add_bus() callback for root bus Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 15/27] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 16/27] PCI: dwc: Convert to use pci_host_probe() Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 17/27] PCI: dwc: Remove root_bus pointer Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 18/27] PCI: dwc: Remove storing of PCI resources Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 19/27] PCI: dwc: Simplify config space handling Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 20/27] PCI: dwc/keystone: Drop duplicated 'num-viewport' Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 21/27] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 22/27] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 23/27] PCI: dwc/meson: Drop unnecessary RC config space initialization Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 24/27] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 25/27] PCI: dwc/qcom: Use common PCI register definitions Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` [RFC 26/27] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring
2020-08-03 21:01 ` Rob Herring [this message]
2020-08-03 21:01 ` [RFC 27/27] PCI: dwc/tegra: Use common Designware port logic register definitions Rob Herring
2020-08-03 21:01 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200803210116.3132633-28-robh@kernel.org \
--to=robh@kernel.org \
--cc=bhelgaas@google.com \
--cc=bjorn.andersson@linaro.org \
--cc=festevam@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=hayashi.kunihiko@socionext.com \
--cc=hongxing.zhu@nxp.com \
--cc=jesper.nilsson@axis.com \
--cc=jingoohan1@gmail.com \
--cc=jonathanh@nvidia.com \
--cc=jonnyc@amazon.com \
--cc=kernel@pengutronix.de \
--cc=kgene@kernel.org \
--cc=khilman@baylibre.com \
--cc=kishon@ti.com \
--cc=krzk@kernel.org \
--cc=l.stach@pengutronix.de \
--cc=linux-amlogic@lists.infradead.org \
--cc=linux-arm-kernel@axis.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-imx@nxp.com \
--cc=linux-omap@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=m-karicheri2@ti.com \
--cc=pratyush.anand@gmail.com \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
--cc=songxiaowei@hisilicon.com \
--cc=svarbanov@mm-sol.com \
--cc=thierry.reding@gmail.com \
--cc=wangbinghui@hisilicon.com \
--cc=yamada.masahiro@socionext.com \
--cc=yue.wang@Amlogic.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.