From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [RFC v3 61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Date: Thu, 6 Aug 2020 18:46:58 +0800 [thread overview]
Message-ID: <20200806104709.13235-62-frank.chang@sifive.com> (raw)
In-Reply-To: <20200806104709.13235-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 6 ------
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.inc.c | 2 --
target/riscv/vector_helper.c | 13 -------------
4 files changed, 23 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ac655b8f274..a9ec14c49ad 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -963,12 +963,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 99320705cca..994ef3031b5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -553,8 +553,6 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
-vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
-vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 1914e547466..718a8834962 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2753,7 +2753,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
@@ -2769,7 +2768,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 920c2aaf98c..359ed6605c6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3901,19 +3901,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
-static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare_quiet(a, b, s);
- return compare == float_relation_unordered;
-}
-
-GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
-
/* Vector Floating-Point Classify Instruction */
#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, void *vs2, int i) \
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [RFC v3 61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Date: Thu, 6 Aug 2020 18:46:58 +0800 [thread overview]
Message-ID: <20200806104709.13235-62-frank.chang@sifive.com> (raw)
In-Reply-To: <20200806104709.13235-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 6 ------
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.inc.c | 2 --
target/riscv/vector_helper.c | 13 -------------
4 files changed, 23 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ac655b8f274..a9ec14c49ad 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -963,12 +963,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 99320705cca..994ef3031b5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -553,8 +553,6 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
-vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
-vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 1914e547466..718a8834962 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2753,7 +2753,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
@@ -2769,7 +2768,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 920c2aaf98c..359ed6605c6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3901,19 +3901,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
-static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s)
-{
- FloatRelation compare = float16_compare_quiet(a, b, s);
- return compare == float_relation_unordered;
-}
-
-GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
-
/* Vector Floating-Point Classify Instruction */
#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, void *vs2, int i) \
--
2.17.1
next prev parent reply other threads:[~2020-08-06 11:54 UTC|newest]
Thread overview: 181+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-06 10:45 [RFC v3 00/71] target/riscv: support vector extension v1.0 frank.chang
2020-08-06 10:45 ` [RFC v3 01/71] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2020-08-06 10:45 ` frank.chang
2020-08-06 10:45 ` [RFC v3 02/71] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2020-08-06 10:45 ` frank.chang
2020-08-06 10:46 ` [RFC v3 03/71] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 04/71] target/riscv: rvv-1.0: add sstatus " frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 05/71] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 18:04 ` Richard Henderson
2020-08-06 18:04 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 18:08 ` Richard Henderson
2020-08-06 18:08 ` Richard Henderson
2020-08-06 18:30 ` Richard Henderson
2020-08-06 18:30 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 08/71] target/riscv: rvv-1.0: add vcsr register frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 09/71] target/riscv: rvv-1.0: add vlenb register frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 18:28 ` Richard Henderson
2020-08-06 18:28 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 11/71] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 18:36 ` Richard Henderson
2020-08-06 18:36 ` Richard Henderson
2020-08-14 3:12 ` Frank Chang
2020-08-14 3:12 ` Frank Chang
2020-08-06 10:46 ` [RFC v3 13/71] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 19:08 ` Richard Henderson
2020-08-06 19:08 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 14/71] target/riscv: rvv-1.0: update check functions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 22:54 ` Richard Henderson
2020-08-06 22:54 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 16/71] target/riscv: add fp16 nan-box check generator function frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 22:57 ` Richard Henderson
2020-08-06 22:57 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 17/71] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 22:58 ` Richard Henderson
2020-08-06 22:58 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 23:00 ` Richard Henderson
2020-08-06 23:00 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 19/71] target/riscv: rvv-1.0: configure instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 23:40 ` Richard Henderson
2020-08-06 23:40 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 20/71] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 21/71] target/riscv: rvv-1.0: index " frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 23/71] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 24/71] target/riscv: rvv-1.0: amo operations frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 25/71] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-07 0:03 ` Richard Henderson
2020-08-07 0:03 ` Richard Henderson
2020-08-14 2:48 ` Frank Chang
2020-08-14 2:48 ` Frank Chang
2020-08-14 18:36 ` Richard Henderson
2020-08-14 18:36 ` Richard Henderson
2020-08-15 2:25 ` Frank Chang
2020-08-15 2:25 ` Frank Chang
2020-08-15 2:52 ` Frank Chang
2020-08-15 2:52 ` Frank Chang
2020-08-15 5:29 ` Richard Henderson
2020-08-15 5:29 ` Richard Henderson
2020-08-15 21:59 ` Frank Chang
2020-08-15 21:59 ` Frank Chang
2020-08-06 10:46 ` [RFC v3 27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 29/71] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 33/71] target/riscv: rvv-1.0: iota instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 34/71] target/riscv: rvv-1.0: element index instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 37/71] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 38/71] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 39/71] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 40/71] target/riscv: rvv-1.0: whole register " frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 41/71] target/riscv: rvv-1.0: integer extension instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 42/71] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 47/71] target/riscv: rvv-1.0: add Zvqmac extension frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 48/71] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 50/71] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 51/71] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 52/71] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 54/71] target/riscv: rvv-1.0: slide instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 55/71] target/riscv: rvv-1.0: floating-point " frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 56/71] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 57/71] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 58/71] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 59/71] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 60/71] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` frank.chang [this message]
2020-08-06 10:46 ` [RFC v3 61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2020-08-06 10:46 ` [RFC v3 62/71] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:47 ` [RFC v3 63/71] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 64/71] target/riscv: introduce floating-point rounding mode enum frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 65/71] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 66/71] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 67/71] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 68/71] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 69/71] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 70/71] target/riscv: gdb: support vector registers for rv64 frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 71/71] target/riscv: gdb: support vector registers for rv32 frank.chang
2020-08-06 10:47 ` frank.chang
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