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From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [cip-dev] [PATCH 22/36] pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
Date: Fri, 21 Aug 2020 10:42:58 +0100	[thread overview]
Message-ID: <20200821094312.3249-23-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com>

[-- Attachment #1: Type: text/plain, Size: 3254 bytes --]

From: Marek Vasut <marek.vasut+renesas@gmail.com>

commit d92ee9cf8ec8d7fe1d7dbc4b3ee459419b1e5533 upstream.

The TDSELCTRL register is responsible for configuring the SDHI/MMC clock
return path delay and may be adjusted by the bootloader. Retain the value
across suspend/resume to prevent hardware instability after resume.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[Biju: Removed R8A77970 and R8A77980 related changes]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c |  2 ++
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c     |  2 ++
 drivers/pinctrl/sh-pfc/pfc-r8a77965.c    |  2 ++
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c    | 10 ++++++++++
 4 files changed, 16 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 897b7923074f..d92c979dfb98 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -5521,10 +5521,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
 
 enum ioctrl_regs {
 	POCCTRL,
+	TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
 	[POCCTRL] = { 0xe6060380, },
+	[TDSELCTRL] = { 0xe60603c0, },
 	{ /* sentinel */ },
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 8edeb4d823f0..944dfd943541 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -5872,10 +5872,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
 
 enum ioctrl_regs {
 	POCCTRL,
+	TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
 	[POCCTRL] = { 0xe6060380, },
+	[TDSELCTRL] = { 0xe60603c0, },
 	{ /* sentinel */ },
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 816341230c08..6616f5210b9d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -6126,10 +6126,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
 
 enum ioctrl_regs {
 	POCCTRL,
+	TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
 	[POCCTRL] = { 0xe6060380, },
+	[TDSELCTRL] = { 0xe60603c0, },
 	{ /* sentinel */ },
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 104ba4b51c9f..20b58e4602c9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -2470,6 +2470,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
 	return bit;
 }
 
+enum ioctrl_regs {
+	TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+	[TDSELCTRL] = { 0xe60603c0, },
+	{ /* sentinel */ },
+};
+
 static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
 	.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
 };
@@ -2489,6 +2498,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
 	.cfg_regs = pinmux_config_regs,
+	.ioctrl_regs = pinmux_ioctrl_regs,
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-- 
2.17.1


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  parent reply	other threads:[~2020-08-21 10:58 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-21  9:42 [cip-dev] [PATCH 00/36] Add Hihope RZ/G2H basic board support Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 01/36] dt-bindings: power: Add r8a774e1 SYSC power domain definitions Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 02/36] dt-bindings: power: renesas,rcar-sysc: Document r8a774e1 SYSC binding Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 03/36] soc: renesas: rcar-sysc: Add r8a774e1 support Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 04/36] soc: renesas: Add Renesas R8A774E1 config option Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 05/36] dt-bindings: arm: renesas: Document RZ/G2H SoC DT bindings Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 06/36] soc: renesas: Identify RZ/G2H Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 07/36] dt-bindings: reset: rcar-rst: Document r8a774e1 reset module Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 08/36] soc: renesas: rcar-rst: Add support for RZ/G2H Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 09/36] clk: renesas: rcar-gen3: Add RPC clocks Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 10/36] clk: renesas: Add r8a774e1 CPG Core Clock Definitions Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 11/36] clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 12/36] clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 13/36] clk: renesas: rzg2: Mark RWDT clocks as critical Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 14/36] dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 15/36] clk: renesas: cpg-mssr: Add r8a774e1 support Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 16/36] arm64: defconfig: Enable R8A774E1 SoC Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 17/36] pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias control Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 18/36] pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 19/36] pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 20/36] pinctrl: sh-pfc: r8a7795: " Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 21/36] pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions Biju Das
2020-08-21  9:42 ` Biju Das [this message]
2020-08-21  9:42 ` [cip-dev] [PATCH 23/36] pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 24/36] pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functions Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 25/36] pinctrl: sh-pfc: r8a7795: " Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 26/36] pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pins Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 27/36] pinctrl: sh-pfc: r8a7795: " Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 28/36] pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3 Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 29/36] pinctrl: sh-pfc: pfc-r8a7795: " Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 30/36] pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 31/36] dt-bindings: pinctrl: sh-pfc: Document r8a774e1 PFC support Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 32/36] pinctrl: sh-pfc: pfc-r8a77951: Add R8A774E1 " Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 33/36] arm64: dts: renesas: Initial r8a774e1 SoC device tree Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 34/36] dt-bindings: arm: renesas: Add HopeRun RZ/G2H boards Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 35/36] arm64: dts: renesas: Add HiHope RZ/G2H main board support Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 36/36] arm64: dts: renesas: Add HiHope RZ/G2H sub " Biju Das
2020-08-23 19:03 ` [cip-dev] [PATCH 00/36] Add Hihope RZ/G2H basic " Pavel Machek
2020-08-23 23:04 ` Nobuhiro Iwamatsu

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